From: Oliver Upton <oliver.upton@linux.dev>
To: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Mark Brown <broonie@kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
Joey Gouly <joey.gouly@arm.com>,
James Morse <james.morse@arm.com>,
stable@vger.kernel.org, Moritz Fischer <moritzf@google.com>,
Pedro Martelletto <martelletto@google.com>,
Jon Masters <jonmasters@google.com>
Subject: Re: [PATCH] arm64: Move storage of idreg overrides into mmuoff section
Date: Fri, 31 Jan 2025 09:03:49 -0800 [thread overview]
Message-ID: <Z50CdVT8fPof-_Zc@linux.dev> (raw)
In-Reply-To: <Z5yseC1kCyTcwlMy@J2N7QTR9R3>
On Fri, Jan 31, 2025 at 10:56:56AM +0000, Mark Rutland wrote:
> On Thu, Jan 30, 2025 at 12:46:15PM -0800, Oliver Upton wrote:
> > There are a few places where the idreg overrides are read w/ the MMU
> > off, for example the VHE and hVHE checks in __finalise_el2. And while
> > the infrastructure gets this _mostly_ right (i.e. does the appropriate
> > cache maintenance), the placement of the data itself is problematic and
> > could share a cache line with something else.
> >
> > Depending on how unforgiving an implementation's handling of mismatched
> > attributes is, this could lead to data corruption. In one observed case,
> > the system_cpucaps shared a line with arm64_sw_feature_override and the
> > cpucaps got nuked after entering the hyp stub...
>
> This doesn't sound right. Non-cacheable/Device reads should not lead to
> corruption of a cached copy regardless of whether that cached copy is
> clean or dirty.
>
> The corruption suggests that either we're performing a *write* with
> mismatched attributes (in which case the use of .mmuoff.data.read below
> isn't quite right), or we have a plan invalidate somewhere without a
> clean (and e.g. something else might need to be moved into
> .mmuoff.data.write).
>
> Seconding Ard's point, I think we need to understand this scenario
> better.
Of course. So the write to the idreg override is fine and gets written
back after cache maintenance.
What's happening afterwards is CPU0 pulls in the line to write to
system_cpucaps which also happens to contain arm64_sw_feature_override.
That line is in UD state when CPU0 calls HVC_FINALISE_EL2 and goes to
EL2 with the MMU off.
__finalise_el2() does a load on arm64_sw_feature_override which goes out
as a ReadNoSnp. I is the only cache state for this request (IHI 0050G
B4.2.1.2) and the SF stops tracking the line, so writeback never
actually goes anywhere.
This patch might have been a touch premature, let me double check a few
things on our side.
--
Thanks,
Oliver
prev parent reply other threads:[~2025-01-31 17:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-30 20:46 [PATCH] arm64: Move storage of idreg overrides into mmuoff section Oliver Upton
2025-01-30 21:48 ` Ard Biesheuvel
2025-01-31 10:56 ` Mark Rutland
2025-01-31 17:03 ` Oliver Upton [this message]
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