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If not > allowed to be accessed, detach the node > > Signed-off-by: Peng Fan > --- > drivers/nvmem/Kconfig | 3 + > drivers/nvmem/imx-ocotp-ele.c | 173 +++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 175 insertions(+), 1 deletion(-) > > diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig > index 8671b7c974b933e147154bb40b5d41b5730518d2..77cc496fd5e0e1afd753534b56fe1f5ef3e3ec55 100644 > --- a/drivers/nvmem/Kconfig > +++ b/drivers/nvmem/Kconfig > @@ -93,6 +93,9 @@ config NVMEM_IMX_OCOTP_ELE > This is a driver for the On-Chip OTP Controller (OCOTP) > available on i.MX SoCs which has ELE. > > + If built as modules, any other driver relying on this working > + as access controller also needs to be a module as well. > + > config NVMEM_IMX_OCOTP_SCU > tristate "i.MX8 SCU On-Chip OTP Controller support" > depends on IMX_SCU > diff --git a/drivers/nvmem/imx-ocotp-ele.c b/drivers/nvmem/imx-ocotp-ele.c > index ca6dd71d8a2e29888c6e556aaea116c1a967cb5f..fe243e4d3377e98a21f660ebad92dbe9bff94330 100644 > --- a/drivers/nvmem/imx-ocotp-ele.c > +++ b/drivers/nvmem/imx-ocotp-ele.c > @@ -5,6 +5,8 @@ > * Copyright 2023 NXP > */ > > +#include > +#include > #include > #include > #include > @@ -27,6 +29,7 @@ struct ocotp_map_entry { > }; > > struct ocotp_devtype_data { > + const struct ocotp_access_gates *access_gates; > u32 reg_off; > char *name; > u32 size; > @@ -36,6 +39,20 @@ struct ocotp_devtype_data { > struct ocotp_map_entry entry[]; > }; > > +#define OCOTP_MAX_NUM_GATE_WORDS 4 > + > +struct access_gate { > + u32 word; > + u32 mask; > +}; > + > +struct ocotp_access_gates { > + u32 num_words; > + u32 words[OCOTP_MAX_NUM_GATE_WORDS]; > + u32 num_gates; > + const struct access_gate *gates; > +}; > + > struct imx_ocotp_priv { > struct device *dev; > void __iomem *base; > @@ -131,6 +148,83 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem, > cell->read_post_process = imx_ocotp_cell_pp; > } > > +static int imx_ele_ocotp_check_access(struct imx_ocotp_priv *priv, u32 id) > +{ > + const struct ocotp_access_gates *access_gates = priv->data->access_gates; > + void __iomem *reg = priv->base + priv->data->reg_off; > + u32 word, mask, val; > + > + if (id >= access_gates->num_gates) { > + dev_err(priv->config.dev, "Index %d too large\n", id); > + return -EACCES; > + } > + > + word = access_gates->gates[id].word; > + mask = access_gates->gates[id].mask; > + > + reg = priv->base + priv->data->reg_off + (word << 2); > + val = readl(reg); > + > + dev_dbg(priv->config.dev, "id:%d word:%d mask:0x%08x\n", id, word, mask); > + /* true means not allow access */ > + if (val & mask) > + return -EACCES; > + > + return 0; > +} > + > +static int imx_ele_ocotp_grant_access(struct imx_ocotp_priv *priv, struct device_node *parent) > +{ > + struct device *dev = priv->config.dev; > + > + for_each_available_child_of_node_scoped(parent, child) { > + struct of_phandle_args args; > + u32 id, idx = 0; > + > + while (!of_parse_phandle_with_args(child, "access-controllers", > + "#access-controller-cells", > + idx++, &args)) { > + of_node_put(args.np); > + if (args.np != dev->of_node) > + continue; > + > + /* Only support one cell */ > + if (args.args_count != 1) { > + dev_err(dev, "wrong args count\n"); > + continue; > + } > + > + id = args.args[0]; > + > + dev_dbg(dev, "Checking node: %pOF gate: %d\n", child, id); > + > + if (imx_ele_ocotp_check_access(priv, id)) { > + of_detach_node(child); > + dev_info(dev, "%pOF: Not granted, device driver will not be probed\n", > + child); > + } > + } > + > + imx_ele_ocotp_grant_access(priv, child); > + } > + > + return 0; > +} > + > +static int imx_ele_ocotp_access_control(struct imx_ocotp_priv *priv) > +{ > + struct device_node *root __free(device_node) = of_find_node_by_path("/"); > + > + if (!priv->data->access_gates) > + return 0; > + > + /* This should never happen */ > + if (WARN_ON(!root)) > + return -EINVAL; > + > + return imx_ele_ocotp_grant_access(priv, root); > +} > + > static int imx_ele_ocotp_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > @@ -161,14 +255,45 @@ static int imx_ele_ocotp_probe(struct platform_device *pdev) > priv->config.fixup_dt_cell_info = imx_ocotp_fixup_dt_cell_info; > mutex_init(&priv->lock); > > + platform_set_drvdata(pdev, priv); > + > nvmem = devm_nvmem_register(dev, &priv->config); > if (IS_ERR(nvmem)) > return PTR_ERR(nvmem); > > - return 0; > + > + return imx_ele_ocotp_access_control(priv); > } > > +static const struct access_gate imx93_access_gate[] = { > + [IMX93_OCOTP_NPU_GATE] = { .word = 19, .mask = BIT(13) }, > + [IMX93_OCOTP_A550_GATE] = { .word = 19, .mask = BIT(14) }, > + [IMX93_OCOTP_A551_GATE] = { .word = 19, .mask = BIT(15) }, > + [IMX93_OCOTP_M33_GATE] = { .word = 19, .mask = BIT(24) }, > + [IMX93_OCOTP_CAN1_FD_GATE] = { .word = 19, .mask = BIT(28) }, > + [IMX93_OCOTP_CAN2_FD_GATE] = { .word = 19, .mask = BIT(29) }, > + [IMX93_OCOTP_CAN1_GATE] = { .word = 19, .mask = BIT(30) }, > + [IMX93_OCOTP_CAN2_GATE] = { .word = 19, .mask = BIT(31) }, > + [IMX93_OCOTP_USB1_GATE] = { .word = 20, .mask = BIT(3) }, > + [IMX93_OCOTP_USB2_GATE] = { .word = 20, .mask = BIT(4) }, > + [IMX93_OCOTP_ENET1_GATE] = { .word = 20, .mask = BIT(5) }, > + [IMX93_OCOTP_ENET2_GATE] = { .word = 20, .mask = BIT(6) }, > + [IMX93_OCOTP_PXP_GATE] = { .word = 20, .mask = BIT(10) }, > + [IMX93_OCOTP_MIPI_CSI1_GATE] = { .word = 20, .mask = BIT(17) }, > + [IMX93_OCOTP_MIPI_DSI1_GATE] = { .word = 20, .mask = BIT(19) }, > + [IMX93_OCOTP_LVDS1_GATE] = { .word = 20, .mask = BIT(24) }, > + [IMX93_OCOTP_ADC1_GATE] = { .word = 21, .mask = BIT(7) }, > +}; > + > +static const struct ocotp_access_gates imx93_access_gates_info = { > + .num_words = 3, > + .words = {19, 20, 21}, > + .num_gates = ARRAY_SIZE(imx93_access_gate), > + .gates = imx93_access_gate, > +}; > + > static const struct ocotp_devtype_data imx93_ocotp_data = { > + .access_gates = &imx93_access_gates_info, > .reg_off = 0x8000, > .reg_read = imx_ocotp_reg_read, > .size = 2048, > @@ -183,7 +308,53 @@ static const struct ocotp_devtype_data imx93_ocotp_data = { > }, > }; > > +static const struct access_gate imx95_access_gate[] = { > + [IMX95_OCOTP_CANFD1_GATE] = { .word = 17, .mask = BIT(20) }, > + [IMX95_OCOTP_CANFD2_GATE] = { .word = 17, .mask = BIT(21) }, > + [IMX95_OCOTP_CANFD3_GATE] = { .word = 17, .mask = BIT(22) }, > + [IMX95_OCOTP_CANFD4_GATE] = { .word = 17, .mask = BIT(23) }, > + [IMX95_OCOTP_CANFD5_GATE] = { .word = 17, .mask = BIT(24) }, > + [IMX95_OCOTP_CAN1_GATE] = { .word = 17, .mask = BIT(25) }, > + [IMX95_OCOTP_CAN2_GATE] = { .word = 17, .mask = BIT(26) }, > + [IMX95_OCOTP_CAN3_GATE] = { .word = 17, .mask = BIT(27) }, > + [IMX95_OCOTP_CAN4_GATE] = { .word = 17, .mask = BIT(28) }, > + [IMX95_OCOTP_CAN5_GATE] = { .word = 17, .mask = BIT(29) }, > + [IMX95_OCOTP_NPU_GATE] = { .word = 18, .mask = BIT(0) }, > + [IMX95_OCOTP_A550_GATE] = { .word = 18, .mask = BIT(1) }, > + [IMX95_OCOTP_A551_GATE] = { .word = 18, .mask = BIT(2) }, > + [IMX95_OCOTP_A552_GATE] = { .word = 18, .mask = BIT(3) }, > + [IMX95_OCOTP_A553_GATE] = { .word = 18, .mask = BIT(4) }, > + [IMX95_OCOTP_A554_GATE] = { .word = 18, .mask = BIT(5) }, > + [IMX95_OCOTP_A555_GATE] = { .word = 18, .mask = BIT(6) }, > + [IMX95_OCOTP_M7_GATE] = { .word = 18, .mask = BIT(9) }, > + [IMX95_OCOTP_DCSS_GATE] = { .word = 18, .mask = BIT(22) }, > + [IMX95_OCOTP_LVDS1_GATE] = { .word = 18, .mask = BIT(27) }, > + [IMX95_OCOTP_ISP_GATE] = { .word = 18, .mask = BIT(29) }, > + [IMX95_OCOTP_USB1_GATE] = { .word = 19, .mask = BIT(2) }, > + [IMX95_OCOTP_USB2_GATE] = { .word = 19, .mask = BIT(3) }, > + [IMX95_OCOTP_NETC_GATE] = { .word = 19, .mask = BIT(4) }, > + [IMX95_OCOTP_PCIE1_GATE] = { .word = 19, .mask = BIT(6) }, > + [IMX95_OCOTP_PCIE2_GATE] = { .word = 19, .mask = BIT(7) }, > + [IMX95_OCOTP_ADC1_GATE] = { .word = 19, .mask = BIT(8) }, > + [IMX95_OCOTP_EARC_RX_GATE] = { .word = 19, .mask = BIT(11) }, > + [IMX95_OCOTP_GPU3D_GATE] = { .word = 19, .mask = BIT(16) }, > + [IMX95_OCOTP_VPU_GATE] = { .word = 19, .mask = BIT(17) }, > + [IMX95_OCOTP_JPEG_ENC_GATE] = { .word = 19, .mask = BIT(18) }, > + [IMX95_OCOTP_JPEG_DEC_GATE] = { .word = 19, .mask = BIT(19) }, > + [IMX95_OCOTP_MIPI_CSI1_GATE] = { .word = 19, .mask = BIT(21) }, > + [IMX95_OCOTP_MIPI_CSI2_GATE] = { .word = 19, .mask = BIT(22) }, > + [IMX95_OCOTP_MIPI_DSI1_GATE] = { .word = 19, .mask = BIT(23) }, > +}; In another thread https://lore.kernel.org/imx/173828013202.1872493.8212881147597194221.robh@kernel.org/T/#mce7b8226138d0523b602b69de679f3857fd86706 Suggest #define IMX95_OCOTP_CANFD1_GATE 17 0x100000 #access-controller-cells = <2> So we can remove these static data in driver. If want validate input data, we just define low..high region and a validate mask to check it. Frank > + > +static const struct ocotp_access_gates imx95_access_gates_info = { > + .num_words = 3, > + .words = {17, 18, 19}, > + .num_gates = ARRAY_SIZE(imx95_access_gate), > + .gates = imx95_access_gate, > +}; > + > static const struct ocotp_devtype_data imx95_ocotp_data = { > + .access_gates = &imx95_access_gates_info, > .reg_off = 0x8000, > .reg_read = imx_ocotp_reg_read, > .size = 2048, > > -- > 2.37.1 >