From: Mark Rutland <mark.rutland@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>, Fuad Tabba <tabba@google.com>
Subject: Re: [PATCH 03/18] KVM: arm64: Handle trapping of FEAT_LS64* instructions
Date: Tue, 11 Feb 2025 12:28:10 +0000 [thread overview]
Message-ID: <Z6tCWmsZxQZw4nmR@J2N7QTR9R3> (raw)
In-Reply-To: <20250210184150.2145093-4-maz@kernel.org>
On Mon, Feb 10, 2025 at 06:41:34PM +0000, Marc Zyngier wrote:
> We generally don't expect FEAT_LS64* instructions to trap, unless
> they are trapped by a guest hypervisor.
>
> Otherwise, this is just the guest playing tricks on us by using
> an instruction that isn't advertised, which we handle with a well
> deserved UNDEF.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/kvm/handle_exit.c | 64 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
> index 512d152233ff2..4f8354bf7dc5f 100644
> --- a/arch/arm64/kvm/handle_exit.c
> +++ b/arch/arm64/kvm/handle_exit.c
> @@ -294,6 +294,69 @@ static int handle_svc(struct kvm_vcpu *vcpu)
> return 1;
> }
>
> +static int handle_ls64b(struct kvm_vcpu *vcpu)
Structurally this looks good. As noted on patch 2, I think that
naming-wise this should be more general, e.g. handle_other_insn().
Mark.
> +{
> + struct kvm *kvm = vcpu->kvm;
> + u64 esr = kvm_vcpu_get_esr(vcpu);
> + u64 iss = ESR_ELx_ISS(esr);
> + bool allowed;
> +
> + switch (iss) {
> + case ESR_ELx_ISS_ST64BV:
> + allowed = kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_V);
> + break;
> + case ESR_ELx_ISS_ST64BV0:
> + allowed = kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA);
> + break;
> + case ESR_ELx_ISS_LDST64B:
> + allowed = kvm_has_feat(kvm, ID_AA64ISAR1_EL1, LS64, LS64);
> + break;
> + default:
> + /* Clearly, we're missing something. */
> + goto unknown_trap;
> + }
> +
> + if (!allowed)
> + goto undef;
> +
> + if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) {
> + u64 hcrx = __vcpu_sys_reg(vcpu, HCRX_EL2);
> + bool fwd;
> +
> + switch (iss) {
> + case ESR_ELx_ISS_ST64BV:
> + fwd = !(hcrx & HCRX_EL2_EnASR);
> + break;
> + case ESR_ELx_ISS_ST64BV0:
> + fwd = !(hcrx & HCRX_EL2_EnAS0);
> + break;
> + case ESR_ELx_ISS_LDST64B:
> + fwd = !(hcrx & HCRX_EL2_EnALS);
> + break;
> + default:
> + /* We don't expect to be here */
> + fwd = false;
> + }
> +
> + if (fwd) {
> + kvm_inject_nested_sync(vcpu, esr);
> + return 1;
> + }
> + }
> +
> +unknown_trap:
> + /*
> + * If we land here, something must be very wrong, because we
> + * have no idea why we trapped at all. Warn and undef as a
> + * fallback.
> + */
> + WARN_ON(1);
> +
> +undef:
> + kvm_inject_undefined(vcpu);
> + return 1;
> +}
> +
> static exit_handle_fn arm_exit_handlers[] = {
> [0 ... ESR_ELx_EC_MAX] = kvm_handle_unknown_ec,
> [ESR_ELx_EC_WFx] = kvm_handle_wfx,
> @@ -303,6 +366,7 @@ static exit_handle_fn arm_exit_handlers[] = {
> [ESR_ELx_EC_CP14_LS] = kvm_handle_cp14_load_store,
> [ESR_ELx_EC_CP10_ID] = kvm_handle_cp10_id,
> [ESR_ELx_EC_CP14_64] = kvm_handle_cp14_64,
> + [ESR_ELx_EC_LS64B] = handle_ls64b,
> [ESR_ELx_EC_HVC32] = handle_hvc,
> [ESR_ELx_EC_SMC32] = handle_smc,
> [ESR_ELx_EC_HVC64] = handle_hvc,
> --
> 2.39.2
>
next prev parent reply other threads:[~2025-02-11 13:05 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 18:41 [PATCH 00/18] KVM: arm64: Revamp Fine Grained Trap handling Marc Zyngier
2025-02-10 18:41 ` [PATCH 01/18] arm64: Add ID_AA64ISAR1_EL1.LS64 encoding for FEAT_LS64WB Marc Zyngier
2025-02-10 18:41 ` [PATCH 02/18] arm64: Add syndrome information for trapped LD64B/ST64B{,V,V0} Marc Zyngier
2025-02-11 12:23 ` Mark Rutland
2025-02-10 18:41 ` [PATCH 03/18] KVM: arm64: Handle trapping of FEAT_LS64* instructions Marc Zyngier
2025-02-11 12:28 ` Mark Rutland [this message]
2025-03-04 14:36 ` Fuad Tabba
2025-03-04 15:25 ` Marc Zyngier
2025-03-04 15:47 ` Marc Zyngier
2025-02-10 18:41 ` [PATCH 04/18] KVM: arm64: Restrict ACCDATA_EL1 undef to FEAT_ST64_ACCDATA being disabled Marc Zyngier
2025-02-10 18:41 ` [PATCH 05/18] KVM: arm64: Don't treat HCRX_EL2 as a FGT register Marc Zyngier
2025-02-10 18:41 ` [PATCH 06/18] KVM: arm64: Plug FEAT_GCS handling Marc Zyngier
2025-02-11 12:36 ` Mark Rutland
2025-02-11 13:35 ` Marc Zyngier
2025-02-11 13:47 ` Mark Rutland
2025-02-10 18:41 ` [PATCH 07/18] KVM: arm64: Compute FGT masks from KVM's own FGT tables Marc Zyngier
2025-03-04 16:55 ` Fuad Tabba
2025-03-10 11:42 ` Marc Zyngier
2025-03-11 19:10 ` Marc Zyngier
2025-02-10 18:41 ` [PATCH 08/18] KVM: arm64: Add description of FGT bits leading to EC!=0x18 Marc Zyngier
2025-02-10 18:41 ` [PATCH 09/18] KVM: arm64: Use computed masks as sanitisers for FGT registers Marc Zyngier
2025-02-10 18:41 ` [PATCH 10/18] KVM: arm64: Unconditionally configure fine-grain traps Marc Zyngier
2025-02-10 18:41 ` [PATCH 11/18] KVM: arm64: Propagate FGT masks to the nVHE hypervisor Marc Zyngier
2025-02-10 18:41 ` [PATCH 12/18] KVM: arm64: Use computed FGT masks to setup FGT registers Marc Zyngier
2025-02-10 18:41 ` [PATCH 13/18] KVM: arm64: Remove most hand-crafted masks for " Marc Zyngier
2025-02-10 18:41 ` [PATCH 14/18] KVM: arm64: Use KVM-specific HCRX_EL2 RES0 mask Marc Zyngier
2025-02-10 18:41 ` [PATCH 15/18] KVM: arm64: Handle PSB CSYNC traps Marc Zyngier
2025-02-10 18:41 ` [PATCH 16/18] KVM: arm64: Switch to table-driven FGU configuration Marc Zyngier
2025-02-10 18:41 ` [PATCH 17/18] KVM: arm64: Validate FGT register descriptions against RES0 masks Marc Zyngier
2025-02-10 18:41 ` [PATCH 18/18] KVM: arm64: Use FGT feature maps to drive RES0 bits Marc Zyngier
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