* [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs
@ 2025-01-13 11:05 Ciprian Costea
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Ciprian Costea @ 2025-01-13 11:05 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
This patchset aims to add two changes to the S32G2/S32G3 dtsi support:
- Adding I2C dts support for S32G SoC based boards
- Centralize the common part of 'S32G-EVB' and 'S32G-RDB' board revisions
into dtsi files. This refactor will serve I2C in this patchset, but in the
future it will also be used for other modules such as : FlexCAN and DSPI.
Changes in V5:
- Updated several commit titles and descriptions.
- Moved 'reg' dtsi node entry after 'compatible'.
- Squashed commit 3/4.
- Changed 'ina231' dtsi node name to 'current-sensor'.
Changes in V4:
- Moved I2C nodes '#address-size' and '#address-cells' entries from board
common level to S32G2/S32G3 SoC level.
Changes in V3:
- Separated patchset into multiple stages: common 'I2C' dts entries, board
'I2C' dts entries and the introduction of common 'S32GXXXA-EVB/RDB' dtsi.
- Added missing changelog for V2 of this patchset
Changes in V2:
- Moved I2C end device '#address-size' and '#address-cells' entries from
board dts to common 's32gxxxa-evb/rdb' common dtsi.
Ciprian Marian Costea (3):
arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 +++++++
.../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
.../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 +++++++
.../boot/dts/freescale/s32g399a-rdb3.dts | 9 ++
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
.../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
7 files changed, 398 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
--
2.45.2
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
@ 2025-01-13 11:05 ` Ciprian Costea
2025-01-15 15:28 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-01-13 11:05 ` [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Ciprian Costea
` (3 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Ciprian Costea @ 2025-01-13 11:05 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Add I2C[0..2] for S32G2 and S32G3 SoCs.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 ++++++++++++++++++++++++
2 files changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 7be430b78c83..beae4d5cf54e 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -333,6 +333,39 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ i2c0: i2c@401e4000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x401e4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c1: i2c@401e8000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x401e8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c2: i2c@401ec000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x401ec000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
uart2: serial@402bc000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
@@ -341,6 +374,28 @@ uart2: serial@402bc000 {
status = "disabled";
};
+ i2c3: i2c@402d8000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x402d8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c4: i2c@402dc000 {
+ compatible = "nxp,s32g2-i2c";
+ reg = <0x402dc000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 6c572ffe37ca..79b38cd8b142 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -390,6 +390,42 @@ uart1: serial@401cc000 {
status = "disabled";
};
+ i2c0: i2c@401e4000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401e4000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c1: i2c@401e8000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401e8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c2: i2c@401ec000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x401ec000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
uart2: serial@402bc000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
@@ -398,6 +434,30 @@ uart2: serial@402bc000 {
status = "disabled";
};
+ i2c3: i2c@402d8000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x402d8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ i2c4: i2c@402dc000 {
+ compatible = "nxp,s32g3-i2c",
+ "nxp,s32g2-i2c";
+ reg = <0x402dc000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 40>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
@ 2025-01-13 11:05 ` Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-01-13 11:05 ` [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
` (2 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Ciprian Costea @ 2025-01-13 11:05 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3
RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts
file. Prepare to add other modules such as FlexCAN, DSPI easily in the
future.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
.../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
.../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
.../boot/dts/freescale/s32g399a-rdb3.dts | 1 +
.../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
.../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
5 files changed, 275 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index b9a119eea2b7..c4a195dd67bf 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "s32g2.dtsi"
+#include "s32gxxxa-evb.dtsi"
/ {
model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index aaa61a8ad0da..b5ba51696f43 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "s32g2.dtsi"
+#include "s32gxxxa-rdb.dtsi"
/ {
model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
index 828e353455b5..94f531be4017 100644
--- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
+++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "s32g3.dtsi"
+#include "s32gxxxa-rdb.dtsi"
/ {
model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
new file mode 100644
index 000000000000..a44eff28073a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2024 NXP
+ *
+ * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
+ * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
+ * Larisa Grigore <larisa.grigore@nxp.com>
+ */
+
+&pinctrl {
+ i2c0_pins: i2c0-pins {
+ i2c0-grp0 {
+ pinmux = <0x101>, <0x111>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-grp1 {
+ pinmux = <0x2352>, <0x2362>;
+ };
+ };
+
+ i2c0_gpio_pins: i2c0-gpio-pins {
+ i2c0-gpio-grp0 {
+ pinmux = <0x100>, <0x110>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-gpio-grp1 {
+ pinmux = <0x2350>, <0x2360>;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ i2c1-grp0 {
+ pinmux = <0x131>, <0x141>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c1-grp1 {
+ pinmux = <0x2cd2>, <0x2ce2>;
+ };
+ };
+
+ i2c1_gpio_pins: i2c1-gpio-pins {
+ i2c1-gpio-grp0 {
+ pinmux = <0x130>, <0x140>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c1-gpio-grp1 {
+ pinmux = <0x2cd0>, <0x2ce0>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-grp0 {
+ pinmux = <0x151>, <0x161>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-grp1 {
+ pinmux = <0x2cf2>, <0x2d02>;
+ };
+ };
+
+ i2c2_gpio_pins: i2c2-gpio-pins {
+ i2c2-gpio-grp0 {
+ pinmux = <0x150>, <0x160>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-gpio-grp1 {
+ pinmux = <0x2cf0>, <0x2d00>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ i2c4-grp0 {
+ pinmux = <0x211>, <0x222>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-grp1 {
+ pinmux = <0x2d43>, <0x2d33>;
+ };
+ };
+
+ i2c4_gpio_pins: i2c4-gpio-pins {
+ i2c4-gpio-grp0 {
+ pinmux = <0x210>, <0x220>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-gpio-grp1 {
+ pinmux = <0x2d40>, <0x2d30>;
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&i2c0_gpio_pins>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&i2c1_gpio_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&i2c4_gpio_pins>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
new file mode 100644
index 000000000000..91fd8dbf2224
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2024 NXP
+ *
+ * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
+ * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
+ * Larisa Grigore <larisa.grigore@nxp.com>
+ */
+
+&pinctrl {
+ i2c0_pins: i2c0-pins {
+ i2c0-grp0 {
+ pinmux = <0x1f2>, <0x201>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-grp1 {
+ pinmux = <0x2353>, <0x2363>;
+ };
+ };
+
+ i2c0_gpio_pins: i2c0-gpio-pins {
+ i2c0-gpio-grp0 {
+ pinmux = <0x1f0>, <0x200>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c0-gpio-grp1 {
+ pinmux = <0x2350>, <0x2360>;
+ };
+ };
+
+ i2c2_pins: i2c2-pins {
+ i2c2-grp0 {
+ pinmux = <0x151>, <0x161>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c2-grp1 {
+ pinmux = <0x2cf2>, <0x2d02>;
+ };
+ };
+
+ i2c2_gpio_pins: i2c2-gpio-pins {
+ i2c2-gpio-grp0 {
+ pinmux = <0x2cf0>, <0x2d00>;
+ };
+
+ i2c2-gpio-grp1 {
+ pinmux = <0x150>, <0x160>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+ };
+
+ i2c4_pins: i2c4-pins {
+ i2c4-grp0 {
+ pinmux = <0x211>, <0x222>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-grp1 {
+ pinmux = <0x2d43>, <0x2d33>;
+ };
+ };
+
+ i2c4_gpio_pins: i2c4-gpio-pins {
+ i2c4-gpio-grp0 {
+ pinmux = <0x210>, <0x220>;
+ drive-open-drain;
+ output-enable;
+ input-enable;
+ slew-rate = <133>;
+ };
+
+ i2c4-gpio-grp1 {
+ pinmux = <0x2d40>, <0x2d30>;
+ };
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&i2c0_gpio_pins>;
+ status = "okay";
+
+ pcal6524: gpio-expander@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&i2c4_gpio_pins>;
+ status = "okay";
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
2025-01-13 11:05 ` [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Ciprian Costea
@ 2025-01-13 11:05 ` Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-02-04 10:12 ` [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Marian Costea
2025-02-18 10:04 ` Shawn Guo
4 siblings, 2 replies; 13+ messages in thread
From: Ciprian Costea @ 2025-01-13 11:05 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Ciprian Marian Costea
From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Add INA231 current sensor for S32G399A-RDB3 boards.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
index 94f531be4017..802f543cae4a 100644
--- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
+++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
@@ -40,6 +40,14 @@ &uart1 {
status = "okay";
};
+&i2c4 {
+ current-sensor@40 {
+ compatible = "ti,ina231";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+};
+
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc0>;
--
2.45.2
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
@ 2025-01-15 15:28 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
1 sibling, 0 replies; 13+ messages in thread
From: Frank Li @ 2025-01-15 15:28 UTC (permalink / raw)
To: Ciprian Costea
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On Mon, Jan 13, 2025 at 01:05:10PM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add I2C[0..2] for S32G2 and S32G3 SoCs.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 ++++++++++++++++++++++++
> 2 files changed, 115 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..beae4d5cf54e 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -333,6 +333,39 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -341,6 +374,28 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g2-usdhc";
> reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 6c572ffe37ca..79b38cd8b142 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -390,6 +390,42 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -398,6 +434,30 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g3-usdhc",
> "nxp,s32g2-usdhc";
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
2025-01-13 11:05 ` [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Ciprian Costea
@ 2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
1 sibling, 0 replies; 13+ messages in thread
From: Frank Li @ 2025-01-15 15:30 UTC (permalink / raw)
To: Ciprian Costea
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On Mon, Jan 13, 2025 at 01:05:11PM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3
> RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts
> file. Prepare to add other modules such as FlexCAN, DSPI easily in the
> future.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
> .../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
> .../boot/dts/freescale/s32g399a-rdb3.dts | 1 +
> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
> 5 files changed, 275 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> index b9a119eea2b7..c4a195dd67bf 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-evb.dtsi"
>
> / {
> model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> index aaa61a8ad0da..b5ba51696f43 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> index 828e353455b5..94f531be4017 100644
> --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> @@ -8,6 +8,7 @@
> /dts-v1/;
>
> #include "s32g3.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> new file mode 100644
> index 000000000000..a44eff28073a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -0,0 +1,150 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x101>, <0x111>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2352>, <0x2362>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x100>, <0x110>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c1_pins: i2c1-pins {
> + i2c1-grp0 {
> + pinmux = <0x131>, <0x141>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-grp1 {
> + pinmux = <0x2cd2>, <0x2ce2>;
> + };
> + };
> +
> + i2c1_gpio_pins: i2c1-gpio-pins {
> + i2c1-gpio-grp0 {
> + pinmux = <0x130>, <0x140>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-gpio-grp1 {
> + pinmux = <0x2cd0>, <0x2ce0>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-1 = <&i2c1_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> new file mode 100644
> index 000000000000..91fd8dbf2224
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x1f2>, <0x201>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2353>, <0x2363>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x1f0>, <0x200>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +
> + pcal6524: gpio-expander@22 {
> + compatible = "nxp,pcal6524";
> + reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
2025-01-13 11:05 ` [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
@ 2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
1 sibling, 0 replies; 13+ messages in thread
From: Frank Li @ 2025-01-15 15:30 UTC (permalink / raw)
To: Ciprian Costea
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On Mon, Jan 13, 2025 at 01:05:12PM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add INA231 current sensor for S32G399A-RDB3 boards.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> index 94f531be4017..802f543cae4a 100644
> --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> @@ -40,6 +40,14 @@ &uart1 {
> status = "okay";
> };
>
> +&i2c4 {
> + current-sensor@40 {
> + compatible = "ti,ina231";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> +};
> +
> &usdhc0 {
> pinctrl-names = "default", "state_100mhz", "state_200mhz";
> pinctrl-0 = <&pinctrl_usdhc0>;
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
` (2 preceding siblings ...)
2025-01-13 11:05 ` [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
@ 2025-02-04 10:12 ` Ciprian Marian Costea
2025-02-04 15:20 ` Frank Li
2025-02-18 10:04 ` Shawn Guo
4 siblings, 1 reply; 13+ messages in thread
From: Ciprian Marian Costea @ 2025-02-04 10:12 UTC (permalink / raw)
To: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
On 1/13/2025 1:05 PM, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> This patchset aims to add two changes to the S32G2/S32G3 dtsi support:
> - Adding I2C dts support for S32G SoC based boards
> - Centralize the common part of 'S32G-EVB' and 'S32G-RDB' board revisions
> into dtsi files. This refactor will serve I2C in this patchset, but in the
> future it will also be used for other modules such as : FlexCAN and DSPI.
>
> Changes in V5:
> - Updated several commit titles and descriptions.
> - Moved 'reg' dtsi node entry after 'compatible'.
> - Squashed commit 3/4.
> - Changed 'ina231' dtsi node name to 'current-sensor'.
>
> Changes in V4:
> - Moved I2C nodes '#address-size' and '#address-cells' entries from board
> common level to S32G2/S32G3 SoC level.
>
> Changes in V3:
> - Separated patchset into multiple stages: common 'I2C' dts entries, board
> 'I2C' dts entries and the introduction of common 'S32GXXXA-EVB/RDB' dtsi.
> - Added missing changelog for V2 of this patchset
>
> Changes in V2:
> - Moved I2C end device '#address-size' and '#address-cells' entries from
> board dts to common 's32gxxxa-evb/rdb' common dtsi.
>
> Ciprian Marian Costea (3):
> arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
> arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
> arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
>
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 +++++++
> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
> .../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 +++++++
> .../boot/dts/freescale/s32g399a-rdb3.dts | 9 ++
> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
> 7 files changed, 398 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>
Hello,
Is there any more feedback on this patchset ? I see that it is hanging
for a while. Just want to check.
Best Regards,
Ciprian
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs
2025-02-04 10:12 ` [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Marian Costea
@ 2025-02-04 15:20 ` Frank Li
0 siblings, 0 replies; 13+ messages in thread
From: Frank Li @ 2025-02-04 15:20 UTC (permalink / raw)
To: Ciprian Marian Costea
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On Tue, Feb 04, 2025 at 12:12:34PM +0200, Ciprian Marian Costea wrote:
> On 1/13/2025 1:05 PM, Ciprian Costea wrote:
> > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> >
> > This patchset aims to add two changes to the S32G2/S32G3 dtsi support:
> > - Adding I2C dts support for S32G SoC based boards
> > - Centralize the common part of 'S32G-EVB' and 'S32G-RDB' board revisions
> > into dtsi files. This refactor will serve I2C in this patchset, but in the
> > future it will also be used for other modules such as : FlexCAN and DSPI.
> >
...
> >
>
> Hello,
>
> Is there any more feedback on this patchset ? I see that it is hanging for a
> while. Just want to check.
After linus create v6.14-rc1 tag, shawn will take care.
Frank
>
> Best Regards,
> Ciprian
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
2025-01-15 15:28 ` Frank Li
@ 2025-02-04 22:01 ` Matthias Brugger
1 sibling, 0 replies; 13+ messages in thread
From: Matthias Brugger @ 2025-02-04 22:01 UTC (permalink / raw)
To: Ciprian Costea, Chester Lin, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
On 13/01/2025 12:05, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add I2C[0..2] for S32G2 and S32G3 SoCs.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 55 ++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 60 ++++++++++++++++++++++++
> 2 files changed, 115 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 7be430b78c83..beae4d5cf54e 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -333,6 +333,39 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g2-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -341,6 +374,28 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g2-usdhc";
> reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 6c572ffe37ca..79b38cd8b142 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -390,6 +390,42 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + i2c0: i2c@401e4000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e4000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@401e8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401e8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c2: i2c@401ec000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x401ec000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> uart2: serial@402bc000 {
> compatible = "nxp,s32g3-linflexuart",
> "fsl,s32v234-linflexuart";
> @@ -398,6 +434,30 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + i2c3: i2c@402d8000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402d8000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> + i2c4: i2c@402dc000 {
> + compatible = "nxp,s32g3-i2c",
> + "nxp,s32g2-i2c";
> + reg = <0x402dc000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 40>;
> + clock-names = "ipg";
> + status = "disabled";
> + };
> +
> usdhc0: mmc@402f0000 {
> compatible = "nxp,s32g3-usdhc",
> "nxp,s32g2-usdhc";
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
2025-01-13 11:05 ` [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Ciprian Costea
2025-01-15 15:30 ` Frank Li
@ 2025-02-04 22:01 ` Matthias Brugger
1 sibling, 0 replies; 13+ messages in thread
From: Matthias Brugger @ 2025-02-04 22:01 UTC (permalink / raw)
To: Ciprian Costea, Chester Lin, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
On 13/01/2025 12:05, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Create common part, s32gxxa-evb.dtsi and s32gxxa-rdb.dtsi, for S32G2/S32G3
> RDB2\3 and EVB G2/G3 boards to avoid copy duplicate part in boards dts
> file. Prepare to add other modules such as FlexCAN, DSPI easily in the
> future.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> .../arm64/boot/dts/freescale/s32g274a-evb.dts | 1 +
> .../boot/dts/freescale/s32g274a-rdb2.dts | 1 +
> .../boot/dts/freescale/s32g399a-rdb3.dts | 1 +
> .../boot/dts/freescale/s32gxxxa-evb.dtsi | 150 ++++++++++++++++++
> .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 122 ++++++++++++++
> 5 files changed, 275 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> create mode 100644 arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> index b9a119eea2b7..c4a195dd67bf 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-evb.dtsi"
>
> / {
> model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> index aaa61a8ad0da..b5ba51696f43 100644
> --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include "s32g2.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
> diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> index 828e353455b5..94f531be4017 100644
> --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> @@ -8,6 +8,7 @@
> /dts-v1/;
>
> #include "s32g3.dtsi"
> +#include "s32gxxxa-rdb.dtsi"
>
> / {
> model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> new file mode 100644
> index 000000000000..a44eff28073a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -0,0 +1,150 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x101>, <0x111>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2352>, <0x2362>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x100>, <0x110>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c1_pins: i2c1-pins {
> + i2c1-grp0 {
> + pinmux = <0x131>, <0x141>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-grp1 {
> + pinmux = <0x2cd2>, <0x2ce2>;
> + };
> + };
> +
> + i2c1_gpio_pins: i2c1-gpio-pins {
> + i2c1-gpio-grp0 {
> + pinmux = <0x130>, <0x140>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c1-gpio-grp1 {
> + pinmux = <0x2cd0>, <0x2ce0>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-1 = <&i2c1_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> new file mode 100644
> index 000000000000..91fd8dbf2224
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2024 NXP
> + *
> + * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> + * Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
> + * Larisa Grigore <larisa.grigore@nxp.com>
> + */
> +
> +&pinctrl {
> + i2c0_pins: i2c0-pins {
> + i2c0-grp0 {
> + pinmux = <0x1f2>, <0x201>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-grp1 {
> + pinmux = <0x2353>, <0x2363>;
> + };
> + };
> +
> + i2c0_gpio_pins: i2c0-gpio-pins {
> + i2c0-gpio-grp0 {
> + pinmux = <0x1f0>, <0x200>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c0-gpio-grp1 {
> + pinmux = <0x2350>, <0x2360>;
> + };
> + };
> +
> + i2c2_pins: i2c2-pins {
> + i2c2-grp0 {
> + pinmux = <0x151>, <0x161>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c2-grp1 {
> + pinmux = <0x2cf2>, <0x2d02>;
> + };
> + };
> +
> + i2c2_gpio_pins: i2c2-gpio-pins {
> + i2c2-gpio-grp0 {
> + pinmux = <0x2cf0>, <0x2d00>;
> + };
> +
> + i2c2-gpio-grp1 {
> + pinmux = <0x150>, <0x160>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> + };
> +
> + i2c4_pins: i2c4-pins {
> + i2c4-grp0 {
> + pinmux = <0x211>, <0x222>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-grp1 {
> + pinmux = <0x2d43>, <0x2d33>;
> + };
> + };
> +
> + i2c4_gpio_pins: i2c4-gpio-pins {
> + i2c4-gpio-grp0 {
> + pinmux = <0x210>, <0x220>;
> + drive-open-drain;
> + output-enable;
> + input-enable;
> + slew-rate = <133>;
> + };
> +
> + i2c4-gpio-grp1 {
> + pinmux = <0x2d40>, <0x2d30>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio_pins>;
> + status = "okay";
> +
> + pcal6524: gpio-expander@22 {
> + compatible = "nxp,pcal6524";
> + reg = <0x22>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c2_pins>;
> + pinctrl-1 = <&i2c2_gpio_pins>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c4_pins>;
> + pinctrl-1 = <&i2c4_gpio_pins>;
> + status = "okay";
> +};
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
2025-01-13 11:05 ` [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
2025-01-15 15:30 ` Frank Li
@ 2025-02-04 22:01 ` Matthias Brugger
1 sibling, 0 replies; 13+ messages in thread
From: Matthias Brugger @ 2025-02-04 22:01 UTC (permalink / raw)
To: Ciprian Costea, Chester Lin, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Pengutronix Kernel Team, linux-arm-kernel, imx, devicetree,
linux-kernel, NXP S32 Linux, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo
On 13/01/2025 12:05, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add INA231 current sensor for S32G399A-RDB3 boards.
>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> index 94f531be4017..802f543cae4a 100644
> --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
> @@ -40,6 +40,14 @@ &uart1 {
> status = "okay";
> };
>
> +&i2c4 {
> + current-sensor@40 {
> + compatible = "ti,ina231";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> +};
> +
> &usdhc0 {
> pinctrl-names = "default", "state_100mhz", "state_200mhz";
> pinctrl-0 = <&pinctrl_usdhc0>;
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
` (3 preceding siblings ...)
2025-02-04 10:12 ` [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Marian Costea
@ 2025-02-18 10:04 ` Shawn Guo
4 siblings, 0 replies; 13+ messages in thread
From: Shawn Guo @ 2025-02-18 10:04 UTC (permalink / raw)
To: Ciprian Costea
Cc: Chester Lin, Matthias Brugger, Ghennadi Procopciuc, Shawn Guo,
Sascha Hauer, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Pengutronix Kernel Team, linux-arm-kernel, imx,
devicetree, linux-kernel, NXP S32 Linux, Christophe Lizzi,
Alberto Ruiz, Enric Balletbo
On Mon, Jan 13, 2025 at 01:05:09PM +0200, Ciprian Costea wrote:
> Ciprian Marian Costea (3):
> arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3
> arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support
> arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4
Applied all, thanks!
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-02-18 10:20 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-13 11:05 [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Costea
2025-01-13 11:05 ` [PATCH v5 1/3] arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 Ciprian Costea
2025-01-15 15:28 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-01-13 11:05 ` [PATCH v5 2/3] arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-01-13 11:05 ` [PATCH v5 3/3] arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 Ciprian Costea
2025-01-15 15:30 ` Frank Li
2025-02-04 22:01 ` Matthias Brugger
2025-02-04 10:12 ` [PATCH v5 0/3] add I2C DTS support for S32G2/S32G3 SoCs Ciprian Marian Costea
2025-02-04 15:20 ` Frank Li
2025-02-18 10:04 ` Shawn Guo
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