[PATCH v7 00/10] arm64: dts: Add Arm Morello support

[PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA [1].

This series adds dts support for the Arm Morello System Development
Platform.

[1] https://www.morello-project.org/

To simplify the testing a linux tree rebased on 6.14-rc4 is accessible
at [2].

[2] https://codeberg.org/vincenzo/linux/src/branch/morello/dts/v6

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> 
Cc: Russell King <linux@armlinux.org.uk>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Changes
=======
v7:
  - Rebased on 6.14-rc4.
  - Added review info.
v6:
  - Introduce arm,morello.yml.
  - Split pmu patch.
  - Address review comments.
v5:
  - Add support for fvp.
  - Add support for pmu.
  - Address review comments.
  - Rebase on 6.14-rc1.
v4:
  - Add cache information.
  - Address review comments.
v3:
  - Address review comments.
  - Rebase on 6.13-rc5.
v2:
  - Addressed review comments.
  - Rebased on 6.13-rc4.
  - Renamed arm,morello to arm,morello-sdp for clarity.

Vincenzo Frascino (10):
  arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS
  dt-bindings: arm: Add Morello compatibility
  dt-bindings: arm: Add Morello fvp compatibility
  dt-bindings: arm: Add Rainier compatibility
  dt-bindings: arm-pmu: Add support for ARM Rainier PMU
  perf: arm_pmuv3: Add support for ARM Rainier PMU
  arm64: dts: morello: Add support for common functionalities
  arm64: dts: morello: Add support for soc dts
  arm64: dts: morello: Add support for fvp dts
  MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

 .../devicetree/bindings/arm/arm,morello.yaml  |  35 ++
 .../devicetree/bindings/arm/cpus.yaml         |   1 +
 .../devicetree/bindings/arm/pmu.yaml          |   1 +
 MAINTAINERS                                   |   7 +
 arch/arm64/Kconfig.platforms                  |   5 +-
 arch/arm64/boot/dts/arm/Makefile              |   1 +
 arch/arm64/boot/dts/arm/morello-fvp.dts       |  77 +++++
 arch/arm64/boot/dts/arm/morello-sdp.dts       | 157 +++++++++
 arch/arm64/boot/dts/arm/morello.dtsi          | 323 ++++++++++++++++++
 drivers/perf/arm_pmuv3.c                      |   2 +
 10 files changed, 606 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,morello.yaml
 create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts
 create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts
 create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi

-- 
2.43.0

[PATCH v7 01/10] arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS

[Vincenzo Frascino]

Update the description and contextually the help text of
CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/Kconfig.platforms | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 02f9248f7c84..c468c23b2bba 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -374,13 +374,12 @@ config ARCH_UNIPHIER
 	  This enables support for Socionext UniPhier SoC family.
 
 config ARCH_VEXPRESS
-	bool "ARMv8 software model (Versatile Express)"
+	bool "ARM Ltd Platforms"
 	select GPIOLIB
 	select PM
 	select PM_GENERIC_DOMAINS
 	help
-	  This enables support for the ARMv8 software model (Versatile
-	  Express).
+	  This enables support for the ARM Ltd Platforms.
 
 config ARCH_VISCONTI
 	bool "Toshiba Visconti SoC Family"
-- 
2.43.0

[PATCH v7 02/10] dt-bindings: arm: Add Morello compatibility

[Vincenzo Frascino]

Add compatibility to Arm Morello System Development Platform.

Note: Morello is at the same time the name of an Architecture [1], an SoC
[2] and a Board [2].
To distinguish in between Architecture/SoC and Board we refer to the first
as arm,morello and to the second as arm,morello-sdp.

[1] https://developer.arm.com/Architectures/Morello
[2] https://www.morello-project.org/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 .../devicetree/bindings/arm/arm,morello.yaml  | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/arm,morello.yaml

diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml
new file mode 100644
index 000000000000..b4cfa8d048c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,morello.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Morello Platforms
+
+maintainers:
+  - Vincenzo Frascino <vincenzo.frascino@arm.com>
+
+description: |+
+  The Morello architecture is an experimental extension to Armv8.2-A,
+  which extends the AArch64 state with the principles proposed in
+  version 7 of the Capability Hardware Enhanced RISC Instructions
+  (CHERI) ISA.
+
+  ARM's Morello Platforms are built as a research project to explore
+  capability architectures based on arm.
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Arm Morello System Development Platform
+        items:
+          - const: arm,morello-sdp
+          - const: arm,morello
+
+additionalProperties: true
+
+...
-- 
2.43.0

[PATCH v7 03/10] dt-bindings: arm: Add Morello fvp compatibility

[Vincenzo Frascino]

Add compatibility to Arm Morello Fixed Virtual Platform.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 Documentation/devicetree/bindings/arm/arm,morello.yaml | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/arm,morello.yaml b/Documentation/devicetree/bindings/arm/arm,morello.yaml
index b4cfa8d048c4..e843b97fa485 100644
--- a/Documentation/devicetree/bindings/arm/arm,morello.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,morello.yaml
@@ -23,9 +23,11 @@ properties:
     const: '/'
   compatible:
     oneOf:
-      - description: Arm Morello System Development Platform
+      - description: Arm Morello System Platforms
         items:
-          - const: arm,morello-sdp
+          - enum:
+              - arm,morello-sdp
+              - arm,morello-fvp
           - const: arm,morello
 
 additionalProperties: true
-- 
2.43.0

[PATCH v7 04/10] dt-bindings: arm: Add Rainier compatibility

[Vincenzo Frascino]

The Arm Morello System Development Platform uses Rainier CPUs.

Add compatibility to Rainier.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 73dd73d2d4fa..2e666b2a4dcd 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -177,6 +177,7 @@ properties:
       - arm,neoverse-v2
       - arm,neoverse-v3
       - arm,neoverse-v3ae
+      - arm,rainier
       - brcm,brahma-b15
       - brcm,brahma-b53
       - brcm,vulcan
-- 
2.43.0

[PATCH v7 05/10] dt-bindings: arm-pmu: Add support for ARM Rainier PMU

[Vincenzo Frascino]

Add support for the ARM Rainier CPU core PMU.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 Documentation/devicetree/bindings/arm/pmu.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
index a148ff54f2b8..295963a3cae7 100644
--- a/Documentation/devicetree/bindings/arm/pmu.yaml
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -67,6 +67,7 @@ properties:
           - arm,neoverse-v2-pmu
           - arm,neoverse-v3-pmu
           - arm,neoverse-v3ae-pmu
+          - arm,rainier-pmu
           - brcm,vulcan-pmu
           - cavium,thunder-pmu
           - nvidia,denver-pmu
-- 
2.43.0

[PATCH v7 06/10] perf: arm_pmuv3: Add support for ARM Rainier PMU

[Vincenzo Frascino]

Add support for the ARM Rainier CPU core PMU.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 drivers/perf/arm_pmuv3.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
index 0e360feb3432..3785522a08e7 100644
--- a/drivers/perf/arm_pmuv3.c
+++ b/drivers/perf/arm_pmuv3.c
@@ -1369,6 +1369,7 @@ PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
 PMUV3_INIT_SIMPLE(armv8_neoverse_v2)
 PMUV3_INIT_SIMPLE(armv8_neoverse_v3)
 PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae)
+PMUV3_INIT_SIMPLE(armv8_rainier)
 
 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
 PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
@@ -1416,6 +1417,7 @@ static const struct of_device_id armv8_pmu_of_device_ids[] = {
 	{.compatible = "arm,neoverse-v2-pmu",	.data = armv8_neoverse_v2_pmu_init},
 	{.compatible = "arm,neoverse-v3-pmu",	.data = armv8_neoverse_v3_pmu_init},
 	{.compatible = "arm,neoverse-v3ae-pmu",	.data = armv8_neoverse_v3ae_pmu_init},
+	{.compatible = "arm,rainier-pmu",	.data = armv8_rainier_pmu_init},
 	{.compatible = "cavium,thunder-pmu",	.data = armv8_cavium_thunder_pmu_init},
 	{.compatible = "brcm,vulcan-pmu",	.data = armv8_brcm_vulcan_pmu_init},
 	{.compatible = "nvidia,carmel-pmu",	.data = armv8_nvidia_carmel_pmu_init},
-- 
2.43.0

[PATCH v7 07/10] arm64: dts: morello: Add support for common functionalities

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.

The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
some functionalities that have conveniently been included in
morello.dtsi to avoid duplication.

Introduce morello.dtsi.

Note: Morello fvp will be introduced with a future patch series.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/boot/dts/arm/morello.dtsi | 323 +++++++++++++++++++++++++++
 1 file changed, 323 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi

diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
new file mode 100644
index 000000000000..e35e5e482720
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello.dtsi
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	soc_refclk50mhz: clock-50000000 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+		clock-output-names = "apb_pclk";
+	};
+
+	soc_refclk85mhz: clock-85000000 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <85000000>;
+		clock-output-names = "iofpga:aclk";
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,rainier";
+			reg = <0x0 0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			/* 4 ways set associative */
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <512>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_0>;
+			clocks = <&scmi_dvfs 0>;
+
+			l2_0: l2-cache-0 {
+				compatible = "cache";
+				cache-level = <2>;
+				/* 8 ways set associative */
+				cache-size = <0x100000>;
+				cache-line-size = <64>;
+				cache-sets = <2048>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+
+				l3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-size = <0x100000>;
+					cache-unified;
+				};
+			};
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,rainier";
+			reg = <0x0 0x100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			/* 4 ways set associative */
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <512>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_1>;
+			clocks = <&scmi_dvfs 0>;
+
+			l2_1: l2-cache-1 {
+				compatible = "cache";
+				cache-level = <2>;
+				/* 8 ways set associative */
+				cache-size = <0x100000>;
+				cache-line-size = <64>;
+				cache-sets = <2048>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu2: cpu@10000 {
+			compatible = "arm,rainier";
+			reg = <0x0 0x10000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			/* 4 ways set associative */
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <512>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_2>;
+			clocks = <&scmi_dvfs 1>;
+
+			l2_2: l2-cache-2 {
+				compatible = "cache";
+				cache-level = <2>;
+				/* 8 ways set associative */
+				cache-size = <0x100000>;
+				cache-line-size = <64>;
+				cache-sets = <2048>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+
+		cpu3: cpu@10100 {
+			compatible = "arm,rainier";
+			reg = <0x0 0x10100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			/* 4 ways set associative */
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <512>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <512>;
+			next-level-cache = <&l2_3>;
+			clocks = <&scmi_dvfs 1>;
+
+			l2_3: l2-cache-3 {
+				compatible = "cache";
+				cache-level = <2>;
+				/* 8 ways set associative */
+				cache-size = <0x100000>;
+				cache-line-size = <64>;
+				cache-sets = <2048>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
+		};
+	};
+
+	firmware {
+		interrupt-parent = <&gic>;
+
+		scmi {
+			compatible = "arm,scmi";
+			mbox-names = "tx", "rx";
+			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
+			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_dvfs: protocol@13 {
+				reg = <0x13>;
+				#clock-cells = <1>;
+			};
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+	};
+
+	/* The first bank of memory, memory map is actually provided by UEFI. */
+	memory@80000000 {
+		device_type = "memory";
+		/* [0x80000000-0xffffffff] */
+		reg = <0x00000000 0x80000000 0x0 0x7f000000>;
+	};
+
+	memory@8080000000 {
+		device_type = "memory";
+		/* [0x8080000000-0x83f7ffffff] */
+		reg = <0x00000080 0x80000000 0x3 0x78000000>;
+	};
+
+	pmu {
+		compatible = "arm,rainier-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure-firmware@ff000000 {
+			reg = <0x0 0xff000000 0x0 0x01000000>;
+			no-map;
+		};
+	};
+
+	spe-pmu {
+		compatible = "arm,statistical-profiling-extension-v1";
+		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		interrupt-parent = <&gic>;
+		ranges;
+
+		uart0: serial@2a400000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x0 0x2a400000 0x0 0x1000>;
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>;
+			clock-names = "uartclk", "apb_pclk";
+
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@2c010000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x30000000 0x0 0x10000>,	/* GICD */
+			      <0x0 0x300c0000 0x0 0x80000>;	/* GICR */
+
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+			#interrupt-cells = <3>;
+			interrupt-controller;
+
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			its1: msi-controller@30040000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x30040000 0x0 0x20000>;
+
+				msi-controller;
+				#msi-cells = <1>;
+			};
+
+			its2: msi-controller@30060000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x30060000 0x0 0x20000>;
+
+				msi-controller;
+				#msi-cells = <1>;
+			};
+
+			its_ccix: msi-controller@30080000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x30080000 0x0 0x20000>;
+
+				msi-controller;
+				#msi-cells = <1>;
+			};
+
+			its_pcie: msi-controller@300a0000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x0 0x300a0000 0x0 0x20000>;
+
+				msi-controller;
+				#msi-cells = <1>;
+			};
+		};
+
+		smmu_dp: iommu@2ce00000 {
+			compatible = "arm,smmu-v3";
+			reg = <0x0 0x2ce00000 0x0 0x40000>;
+
+			interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eventq", "gerror", "cmdq-sync";
+			#iommu-cells = <1>;
+		};
+
+		mailbox: mhu@45000000 {
+			compatible = "arm,mhu-doorbell", "arm,primecell";
+			reg = <0x0 0x45000000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <2>;
+			clocks = <&soc_refclk50mhz>;
+			clock-names = "apb_pclk";
+		};
+
+		sram: sram@45200000 {
+			compatible = "mmio-sram";
+			reg = <0x0 0x06000000 0x0 0x8000>;
+			ranges = <0 0x0 0x06000000 0x8000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cpu_scp_hpri0: scp-sram@0 {
+				compatible = "arm,scmi-shmem";
+				reg = <0x0 0x80>;
+			};
+
+			cpu_scp_hpri1: scp-sram@80 {
+				compatible = "arm,scmi-shmem";
+				reg = <0x80 0x80>;
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
-- 
2.43.0

[PATCH v7 08/10] arm64: dts: morello: Add support for soc dts

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.

Introduce Morello SoC dts.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/boot/dts/arm/Makefile        |   1 +
 arch/arm64/boot/dts/arm/morello-sdp.dts | 157 ++++++++++++++++++++++++
 2 files changed, 158 insertions(+)
 create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts

diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index d908e96d7ddc..869667bef7c0 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb
diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts
new file mode 100644
index 000000000000..cee49dee7571
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello-sdp.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ */
+
+/dts-v1/;
+#include "morello.dtsi"
+
+/ {
+	model = "Arm Morello System Development Platform";
+	compatible = "arm,morello-sdp", "arm,morello";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dpu_aclk: clock-350000000 {
+		/* 77.1 MHz derived from 24 MHz reference clock */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <350000000>;
+		clock-output-names = "aclk";
+	};
+
+	dpu_pixel_clk: clock-148500000 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <148500000>;
+		clock-output-names = "pxclk";
+	};
+
+	i2c0: i2c@1c0f0000 {
+		compatible = "cdns,i2c-r1p14";
+		reg = <0x0 0x1c0f0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&dpu_aclk>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clock-frequency = <100000>;
+
+		hdmi_tx: hdmi-transmitter@70 {
+			compatible = "nxp,tda998x";
+			reg = <0x70>;
+			video-ports = <0x234501>;
+			port {
+				tda998x_0_input: endpoint {
+					remote-endpoint = <&dp_pl0_out0>;
+				};
+			};
+		};
+	};
+
+	dp0: display@2cc00000 {
+		compatible = "arm,mali-d32", "arm,mali-d71";
+		reg = <0x0 0x2cc00000 0x0 0x20000>;
+		interrupts = <0 69 4>;
+		clocks = <&dpu_aclk>;
+		clock-names = "aclk";
+		iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
+			 <&smmu_dp 8>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pl0: pipeline@0 {
+			reg = <0>;
+			clocks = <&dpu_pixel_clk>;
+			clock-names = "pxclk";
+			port {
+				dp_pl0_out0: endpoint {
+					remote-endpoint = <&tda998x_0_input>;
+				};
+			};
+		};
+	};
+
+	smmu_ccix: iommu@4f000000 {
+		compatible = "arm,smmu-v3";
+		reg = <0x0 0x4f000000 0x0 0x40000>;
+
+		interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+		msi-parent = <&its1 0>;
+		#iommu-cells = <1>;
+		dma-coherent;
+	};
+
+	smmu_pcie: iommu@4f400000 {
+		compatible = "arm,smmu-v3";
+		reg = <0x0 0x4f400000 0x0 0x40000>;
+
+		interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
+					<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+		msi-parent = <&its2 0>;
+		#iommu-cells = <1>;
+		dma-coherent;
+	};
+
+	pcie_ctlr: pcie@28c0000000 {
+		device_type = "pci";
+		compatible = "pci-host-ecam-generic";
+		reg = <0x28 0xC0000000 0 0x10000000>;
+		ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>,
+				<0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>,
+				<0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>;
+		bus-range = <0 255>;
+		linux,pci-domain = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		dma-coherent;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
+		msi-map = <0 &its_pcie 0 0x10000>;
+		iommu-map = <0 &smmu_pcie 0 0x10000>;
+	};
+
+	ccix_pcie_ctlr: pcie@4fc0000000 {
+		device_type = "pci";
+		compatible = "pci-host-ecam-generic";
+		reg = <0x4f 0xC0000000 0 0x10000000>;
+		ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>,
+				<0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>,
+				<0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>;
+		linux,pci-domain = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		dma-coherent;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
+		msi-map = <0 &its_ccix 0 0x10000>;
+		iommu-map = <0 &smmu_ccix 0 0x10000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.43.0

[PATCH v7 09/10] arm64: dts: morello: Add support for fvp dts

[Vincenzo Frascino]

The Morello architecture is an experimental extension to Armv8.2-A,
which extends the AArch64 state with the principles proposed in
version 7 of the Capability Hardware Enhanced RISC Instructions
(CHERI) ISA.

Introduce Morello fvp dts.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 arch/arm64/boot/dts/arm/Makefile        |  2 +-
 arch/arm64/boot/dts/arm/morello-fvp.dts | 77 +++++++++++++++++++++++++
 2 files changed, 78 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts

diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index 869667bef7c0..f30ee045dc95 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
-dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb
diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts
new file mode 100644
index 000000000000..2072c0b72325
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/morello-fvp.dts
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ */
+
+/dts-v1/;
+#include "morello.dtsi"
+
+/ {
+	model = "Arm Morello Fixed Virtual Platform";
+	compatible = "arm,morello-fvp", "arm,morello";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	bp_refclock24mhz: clock-24000000 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "bp:clock24mhz";
+	};
+
+	block_0: virtio_block@1c170000 {
+		compatible = "virtio,mmio";
+		reg = <0x0 0x1c170000 0x0 0x200>;
+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	net_0: virtio_net@1c180000 {
+		compatible = "virtio,mmio";
+		reg = <0x0 0x1c180000 0x0 0x200>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	rng_0: virtio_rng@1c190000 {
+		compatible = "virtio,mmio";
+		reg = <0x0 0x1c190000 0x0 0x200>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	p9_0: virtio_p9@1c1a0000 {
+		compatible = "virtio,mmio";
+		reg = <0x0 0x1c1a0000 0x0 0x200>;
+		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	kmi_0: kmi@1c150000 {
+		compatible = "arm,pl050", "arm,primecell";
+		reg = <0x0 0x1c150000 0x0 0x1000>;
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
+		clock-names = "KMIREFCLK", "apb_pclk";
+	};
+
+	kmi_1: kmi@1c160000 {
+		compatible = "arm,pl050", "arm,primecell";
+		reg = <0x0 0x1c160000 0x0 0x1000>;
+		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>;
+		clock-names = "KMIREFCLK", "apb_pclk";
+	};
+
+	eth_0: ethernet@1d100000 {
+		compatible = "smsc,lan91c111";
+		reg = <0x0 0x1d100000 0x0 0x10000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.43.0

[PATCH v7 10/10] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

[Vincenzo Frascino]

Add Vincenzo Frascino <vincenzo.frascino@arm.com> as Arm Morello Software
Development Platform Maintainer.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3864d473f52f..6aaef2286de8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2750,6 +2750,13 @@ F:	arch/arm/boot/dts/socionext/milbeaut*
 F:	arch/arm/mach-milbeaut/
 N:	milbeaut
 
+ARM/MORELLO PLATFORM
+M:	Vincenzo Frascino <vincenzo.frascino@arm.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/arm,morello.yaml
+F:	arch/arm64/boot/dts/arm/morello*
+
 ARM/MOXA ART SOC
 M:	Krzysztof Kozlowski <krzk@kernel.org>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.43.0

Re: [PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Mark Rutland]

Hi Vincenzo,

On Fri, Feb 21, 2025 at 06:03:39PM +0000, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA [1].

None of the CHERI stuff is supported upstream, so from upstream's PoV
this is a low-volume dev-board/SoC with an experimental ARMv8.2-A CPU.

> This series adds dts support for the Arm Morello System Development
> Platform.

Do we actually need the dts for this board?

I have one on my desk; it boots vanilla Debian 12 via UEFI + ACPI just
fine, with the Debian 6.1.0-13-arm64 kernel.

Is there something that we can only do with the DT? i.e. some
functionality that isn't exposed via ACPI?

How do you expect this DT to be used?

Mark.

> 
> [1] https://www.morello-project.org/
> 
> To simplify the testing a linux tree rebased on 6.14-rc4 is accessible
> at [2].
> 
> [2] https://codeberg.org/vincenzo/linux/src/branch/morello/dts/v6
> 
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Cc: Sudeep Holla <sudeep.holla@arm.com>
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> 
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Jessica Clarke <jrtc27@jrtc27.com>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> 
> Changes
> =======
> v7:
>   - Rebased on 6.14-rc4.
>   - Added review info.
> v6:
>   - Introduce arm,morello.yml.
>   - Split pmu patch.
>   - Address review comments.
> v5:
>   - Add support for fvp.
>   - Add support for pmu.
>   - Address review comments.
>   - Rebase on 6.14-rc1.
> v4:
>   - Add cache information.
>   - Address review comments.
> v3:
>   - Address review comments.
>   - Rebase on 6.13-rc5.
> v2:
>   - Addressed review comments.
>   - Rebased on 6.13-rc4.
>   - Renamed arm,morello to arm,morello-sdp for clarity.
> 
> Vincenzo Frascino (10):
>   arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS
>   dt-bindings: arm: Add Morello compatibility
>   dt-bindings: arm: Add Morello fvp compatibility
>   dt-bindings: arm: Add Rainier compatibility
>   dt-bindings: arm-pmu: Add support for ARM Rainier PMU
>   perf: arm_pmuv3: Add support for ARM Rainier PMU
>   arm64: dts: morello: Add support for common functionalities
>   arm64: dts: morello: Add support for soc dts
>   arm64: dts: morello: Add support for fvp dts
>   MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer
> 
>  .../devicetree/bindings/arm/arm,morello.yaml  |  35 ++
>  .../devicetree/bindings/arm/cpus.yaml         |   1 +
>  .../devicetree/bindings/arm/pmu.yaml          |   1 +
>  MAINTAINERS                                   |   7 +
>  arch/arm64/Kconfig.platforms                  |   5 +-
>  arch/arm64/boot/dts/arm/Makefile              |   1 +
>  arch/arm64/boot/dts/arm/morello-fvp.dts       |  77 +++++
>  arch/arm64/boot/dts/arm/morello-sdp.dts       | 157 +++++++++
>  arch/arm64/boot/dts/arm/morello.dtsi          | 323 ++++++++++++++++++
>  drivers/perf/arm_pmuv3.c                      |   2 +
>  10 files changed, 606 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/arm/arm,morello.yaml
>  create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts
>  create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts
>  create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
> 
> -- 
> 2.43.0
> 

Re: [PATCH v7 04/10] dt-bindings: arm: Add Rainier compatibility

[Mark Rutland]

On Fri, Feb 21, 2025 at 06:03:43PM +0000, Vincenzo Frascino wrote:
> The Arm Morello System Development Platform uses Rainier CPUs.
> 
> Add compatibility to Rainier.

Where's the TRM? Are there any known errata such that we might need to
know the MIDR, etc?

Mark.

> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> index 73dd73d2d4fa..2e666b2a4dcd 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> @@ -177,6 +177,7 @@ properties:
>        - arm,neoverse-v2
>        - arm,neoverse-v3
>        - arm,neoverse-v3ae
> +      - arm,rainier
>        - brcm,brahma-b15
>        - brcm,brahma-b53
>        - brcm,vulcan
> -- 
> 2.43.0
> 

Re: [PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Vincenzo Frascino]

Hello Mark,

On 21/02/2025 18:54, Mark Rutland wrote:
> Hi Vincenzo,
> 
> On Fri, Feb 21, 2025 at 06:03:39PM +0000, Vincenzo Frascino wrote:
>> The Morello architecture is an experimental extension to Armv8.2-A,
>> which extends the AArch64 state with the principles proposed in
>> version 7 of the Capability Hardware Enhanced RISC Instructions
>> (CHERI) ISA [1].
> 
> None of the CHERI stuff is supported upstream, so from upstream's PoV
> this is a low-volume dev-board/SoC with an experimental ARMv8.2-A CPU.
>

Agreed, I have no plans to upstream Morello support beyond the device tree.

>> This series adds dts support for the Arm Morello System Development
>> Platform.
> 
> Do we actually need the dts for this board?
> 
> I have one on my desk; it boots vanilla Debian 12 via UEFI + ACPI just
> fine, with the Debian 6.1.0-13-arm64 kernel.
> 
> Is there something that we can only do with the DT? i.e. some
> functionality that isn't exposed via ACPI?
> 
> How do you expect this DT to be used?
> 

There are functionalities that are not exposed via ACPI, e.g. gpu, dpu, i2c for
the phy, etc. My aim to have upstream support for all the hardware exposed by
the platform.

Note: This series contains only the basic infrastructure, the plan is add
progressively more features in the future.

Vincenzo

> Mark.
> 
>>
>> [1] https://www.morello-project.org/
>>
>> To simplify the testing a linux tree rebased on 6.14-rc4 is accessible
>> at [2].
>>
>> [2] https://codeberg.org/vincenzo/linux/src/branch/morello/dts/v6
>>
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
>> Cc: Conor Dooley <conor+dt@kernel.org>
>> Cc: Liviu Dudau <liviu.dudau@arm.com>
>> Cc: Sudeep Holla <sudeep.holla@arm.com>
>> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> 
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Jessica Clarke <jrtc27@jrtc27.com>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>>
>> Changes
>> =======
>> v7:
>>   - Rebased on 6.14-rc4.
>>   - Added review info.
>> v6:
>>   - Introduce arm,morello.yml.
>>   - Split pmu patch.
>>   - Address review comments.
>> v5:
>>   - Add support for fvp.
>>   - Add support for pmu.
>>   - Address review comments.
>>   - Rebase on 6.14-rc1.
>> v4:
>>   - Add cache information.
>>   - Address review comments.
>> v3:
>>   - Address review comments.
>>   - Rebase on 6.13-rc5.
>> v2:
>>   - Addressed review comments.
>>   - Rebased on 6.13-rc4.
>>   - Renamed arm,morello to arm,morello-sdp for clarity.
>>
>> Vincenzo Frascino (10):
>>   arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS
>>   dt-bindings: arm: Add Morello compatibility
>>   dt-bindings: arm: Add Morello fvp compatibility
>>   dt-bindings: arm: Add Rainier compatibility
>>   dt-bindings: arm-pmu: Add support for ARM Rainier PMU
>>   perf: arm_pmuv3: Add support for ARM Rainier PMU
>>   arm64: dts: morello: Add support for common functionalities
>>   arm64: dts: morello: Add support for soc dts
>>   arm64: dts: morello: Add support for fvp dts
>>   MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer
>>
>>  .../devicetree/bindings/arm/arm,morello.yaml  |  35 ++
>>  .../devicetree/bindings/arm/cpus.yaml         |   1 +
>>  .../devicetree/bindings/arm/pmu.yaml          |   1 +
>>  MAINTAINERS                                   |   7 +
>>  arch/arm64/Kconfig.platforms                  |   5 +-
>>  arch/arm64/boot/dts/arm/Makefile              |   1 +
>>  arch/arm64/boot/dts/arm/morello-fvp.dts       |  77 +++++
>>  arch/arm64/boot/dts/arm/morello-sdp.dts       | 157 +++++++++
>>  arch/arm64/boot/dts/arm/morello.dtsi          | 323 ++++++++++++++++++
>>  drivers/perf/arm_pmuv3.c                      |   2 +
>>  10 files changed, 606 insertions(+), 3 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/arm/arm,morello.yaml
>>  create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts
>>  create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts
>>  create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
>>
>> -- 
>> 2.43.0
>>

-- 
Regards,
Vincenzo

Re: [PATCH v7 04/10] dt-bindings: arm: Add Rainier compatibility

[Vincenzo Frascino]

Hello Mark,

On 21/02/2025 18:55, Mark Rutland wrote:
> On Fri, Feb 21, 2025 at 06:03:43PM +0000, Vincenzo Frascino wrote:
>> The Arm Morello System Development Platform uses Rainier CPUs.
>>
>> Add compatibility to Rainier.
> 
> Where's the TRM? Are there any known errata such that we might need to
> know the MIDR, etc?
> 

Please find the documents below:
- TRM [0]
- Erratum [1]

This series mainly focuses on basic DT functionalities, but I have plans to
continue with the enablement in future.

Thanks,
Vincenzo

[0] https://developer.arm.com/documentation/102278/latest/
[1] https://developer.arm.com/documentation/SDEN2275302/0000

> Mark.
> 
>>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>>  Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
>> index 73dd73d2d4fa..2e666b2a4dcd 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.yaml
>> +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
>> @@ -177,6 +177,7 @@ properties:
>>        - arm,neoverse-v2
>>        - arm,neoverse-v3
>>        - arm,neoverse-v3ae
>> +      - arm,rainier
>>        - brcm,brahma-b15
>>        - brcm,brahma-b53
>>        - brcm,vulcan
>> -- 
>> 2.43.0
>>

-- 
Regards,
Vincenzo

Re: [PATCH v7 03/10] dt-bindings: arm: Add Morello fvp compatibility

[Rob Herring (Arm)]

On Fri, 21 Feb 2025 18:03:42 +0000, Vincenzo Frascino wrote:
> Add compatibility to Arm Morello Fixed Virtual Platform.
> 
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  Documentation/devicetree/bindings/arm/arm,morello.yaml | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Sudeep Holla]

Hi Mark,

Thanks for raising valid points/concerns.

On Mon, Feb 24, 2025 at 10:08:18AM +0000, Vincenzo Frascino wrote:
> Hello Mark,
>
> On 21/02/2025 18:54, Mark Rutland wrote:
> > Hi Vincenzo,
> >
> > On Fri, Feb 21, 2025 at 06:03:39PM +0000, Vincenzo Frascino wrote:
> >> The Morello architecture is an experimental extension to Armv8.2-A,
> >> which extends the AArch64 state with the principles proposed in
> >> version 7 of the Capability Hardware Enhanced RISC Instructions
> >> (CHERI) ISA [1].
> >
> > None of the CHERI stuff is supported upstream, so from upstream's PoV
> > this is a low-volume dev-board/SoC with an experimental ARMv8.2-A CPU.
> >

I understand and agree with your concerns.

>
> Agreed, I have no plans to upstream Morello support beyond the device tree.
>
> >> This series adds dts support for the Arm Morello System Development
> >> Platform.
> >
> > Do we actually need the dts for this board?
> >
> > I have one on my desk; it boots vanilla Debian 12 via UEFI + ACPI just
> > fine, with the Debian 6.1.0-13-arm64 kernel.
> >
> > Is there something that we can only do with the DT? i.e. some
> > functionality that isn't exposed via ACPI?
> >
> > How do you expect this DT to be used?
> >
>
> There are functionalities that are not exposed via ACPI, e.g. gpu, dpu, i2c for
> the phy, etc. My aim to have upstream support for all the hardware exposed by
> the platform.
>

Does this address some of your concerns ? I do understand some of these
are not well addressed in ACPI and hence people use DT as an alternative.

> Note: This series contains only the basic infrastructure, the plan is add
> progressively more features in the future.
>

I was thinking of queuing this in -next if all the bindings are acked.
Let me know if you still have concerns and would like to avoid getting
these merged. I will hold off then.

--
Regards,
Sudeep

Re: [PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Mark Rutland]

Hi Sudeep,

On Tue, Feb 25, 2025 at 12:07:16PM +0000, Sudeep Holla wrote:
> On Mon, Feb 24, 2025 at 10:08:18AM +0000, Vincenzo Frascino wrote:
> > On 21/02/2025 18:54, Mark Rutland wrote:
> > > On Fri, Feb 21, 2025 at 06:03:39PM +0000, Vincenzo Frascino wrote:
> > >> This series adds dts support for the Arm Morello System Development
> > >> Platform.
> > >
> > > Do we actually need the dts for this board?
> > >
> > > I have one on my desk; it boots vanilla Debian 12 via UEFI + ACPI just
> > > fine, with the Debian 6.1.0-13-arm64 kernel.
> > >
> > > Is there something that we can only do with the DT? i.e. some
> > > functionality that isn't exposed via ACPI?
> > >
> > > How do you expect this DT to be used?
> >
> > There are functionalities that are not exposed via ACPI, e.g. gpu, dpu, i2c for
> > the phy, etc. My aim to have upstream support for all the hardware exposed by
> > the platform.
> 
> Does this address some of your concerns ? I do understand some of these
> are not well addressed in ACPI and hence people use DT as an alternative.

Yep; I'm happy with this so long as there's an actual functional reason
to have the DT, which it seems there is.

It would have been nice for that to be spelled out a bit clearer in the
cover / commit messages, but that's not important and doesn't need a
respin.

> I was thinking of queuing this in -next if all the bindings are acked.
> Let me know if you still have concerns and would like to avoid getting
> these merged. I will hold off then.

No need to hold off.

Sorry for the confusion; I should have been clearer with my questions.

Mark.

Re: [PATCH v7 05/10] dt-bindings: arm-pmu: Add support for ARM Rainier PMU

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> Add support for the ARM Rainier CPU core PMU.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v7 03/10] dt-bindings: arm: Add Morello fvp compatibility

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> Add compatibility to Arm Morello Fixed Virtual Platform.
>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

I see my v6 and v7 patches are mingled. Sorry for any double-review tags.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v7 02/10] dt-bindings: arm: Add Morello compatibility

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> Add compatibility to Arm Morello System Development Platform.
>
> Note: Morello is at the same time the name of an Architecture [1], an SoC
> [2] and a Board [2].
> To distinguish in between Architecture/SoC and Board we refer to the first
> as arm,morello and to the second as arm,morello-sdp.
>
> [1] https://developer.arm.com/Architectures/Morello
> [2] https://www.morello-project.org/
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Re: [PATCH v7 02/10] dt-bindings: arm: Add Morello compatibility

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> Add compatibility to Arm Morello System Development Platform.
>
> Note: Morello is at the same time the name of an Architecture [1], an SoC
> [2] and a Board [2].
> To distinguish in between Architecture/SoC and Board we refer to the first
> as arm,morello and to the second as arm,morello-sdp.
>
> [1] https://developer.arm.com/Architectures/Morello
> [2] https://www.morello-project.org/
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v7 07/10] arm64: dts: morello: Add support for common functionalities

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
>
> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
> some functionalities that have conveniently been included in
> morello.dtsi to avoid duplication.
>
> Introduce morello.dtsi.
>
> Note: Morello fvp will be introduced with a future patch series.
>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v7 08/10] arm64: dts: morello: Add support for soc dts

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
>
> Introduce Morello SoC dts.
>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v7 09/10] arm64: dts: morello: Add support for fvp dts

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
>
> Introduce Morello fvp dts.
>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v7 10/10] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer

[Linus Walleij]

On Fri, Feb 21, 2025 at 7:04 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:

> Add Vincenzo Frascino <vincenzo.frascino@arm.com> as Arm Morello Software
> Development Platform Maintainer.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Sudeep Holla]

On Tue, Feb 25, 2025 at 12:14:31PM +0000, Mark Rutland wrote:
> Hi Sudeep,
> 
> On Tue, Feb 25, 2025 at 12:07:16PM +0000, Sudeep Holla wrote:
> > On Mon, Feb 24, 2025 at 10:08:18AM +0000, Vincenzo Frascino wrote:
> > > On 21/02/2025 18:54, Mark Rutland wrote:
> > > > On Fri, Feb 21, 2025 at 06:03:39PM +0000, Vincenzo Frascino wrote:
> > > >> This series adds dts support for the Arm Morello System Development
> > > >> Platform.
> > > >
> > > > Do we actually need the dts for this board?
> > > >
> > > > I have one on my desk; it boots vanilla Debian 12 via UEFI + ACPI just
> > > > fine, with the Debian 6.1.0-13-arm64 kernel.
> > > >
> > > > Is there something that we can only do with the DT? i.e. some
> > > > functionality that isn't exposed via ACPI?
> > > >
> > > > How do you expect this DT to be used?
> > >
> > > There are functionalities that are not exposed via ACPI, e.g. gpu, dpu, i2c for
> > > the phy, etc. My aim to have upstream support for all the hardware exposed by
> > > the platform.
> > 
> > Does this address some of your concerns ? I do understand some of these
> > are not well addressed in ACPI and hence people use DT as an alternative.
> 
> Yep; I'm happy with this so long as there's an actual functional reason
> to have the DT, which it seems there is.
> 
> It would have been nice for that to be spelled out a bit clearer in the
> cover / commit messages, but that's not important and doesn't need a
> respin.
>

I can add that info in my pull request as it is very valid point. One needs
to know why we are pushing DTS now after couple of years after the boards
are available and why DT over ACPI which is shipped with the device.

> > I was thinking of queuing this in -next if all the bindings are acked.
> > Let me know if you still have concerns and would like to avoid getting
> > these merged. I will hold off then.
> 
> No need to hold off.
> 
> Sorry for the confusion; I should have been clearer with my questions.
> 

No confusion as such, good to ask explicitly and get the motivation for
this series captured on the list. Since I had gone through this motion
even with N1SDP which for some reasons I don't know didn't appear on the
list, I didn't ask it and implicitly assumed similar reasoning.

So, it is good that you asked and got it answered for wider audience here.

-- 
Regards,
Sudeep

Re: [PATCH v7 06/10] perf: arm_pmuv3: Add support for ARM Rainier PMU

[Sudeep Holla]

On Fri, Feb 21, 2025 at 06:03:45PM +0000, Vincenzo Frascino wrote:
> Add support for the ARM Rainier CPU core PMU.
>

I can't take this through Arm SoC as the DTS and dt-bindings changes
are kept separate from the driver changes in their pull request to Linus.

I need to keep the bindings(05/10) and the DTS(07/10) together to avoid
DTC warnings.

So the 2 options I see are:
Defer this driver change until the bindings last upstream.
OR
Just take the perf driver change without the binding via perf tree

For now, I will take all other patches except this.

--
Regards,
Sudeep

Re: [PATCH v7 07/10] arm64: dts: morello: Add support for common functionalities

[Sudeep Holla]

On Fri, Feb 21, 2025 at 06:03:46PM +0000, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
> 
> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
> some functionalities that have conveniently been included in
> morello.dtsi to avoid duplication.
> 
> Introduce morello.dtsi.
> 
> Note: Morello fvp will be introduced with a future patch series.
> 
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
>  arch/arm64/boot/dts/arm/morello.dtsi | 323 +++++++++++++++++++++++++++
>  1 file changed, 323 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
> 
> diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
> new file mode 100644
> +
> +		gic: interrupt-controller@2c010000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x0 0x30000000 0x0 0x10000>,	/* GICD */
> +			      <0x0 0x300c0000 0x0 0x80000>;	/* GICR */

[...]

> +
> +
> +		sram: sram@45200000 {
> +			compatible = "mmio-sram";
> +			reg = <0x0 0x06000000 0x0 0x8000>;
> +			ranges = <0 0x0 0x06000000 0x8000>;
> +

[...]

Not sure if you are not seeing these warnings from DTC. Looks pretty clear
to me. May be you missed or using some old DTC. I don't know why though.
If you agree, I can patch it up with below patch and no need to repost:

morello.dtsi:227.38-272.5: Warning (simple_bus_reg): /soc/interrupt-controller@2c010000: simple-bus unit address format error, expected "30000000"
morello.dtsi:296.23-313.5: Warning (simple_bus_reg): /soc/sram@45200000: simple-bus unit address format error, expected "6000000"
morello.dtsi:227.38-272.5: Warning (simple_bus_reg): /soc/interrupt-controller@2c010000: simple-bus unit address format error, expected "30000000"
morello.dtsi:296.23-313.5: Warning (simple_bus_reg): /soc/sram@45200000: simple-bus unit address format error, expected "6000000"

Regards,
Sudeep

-->8

diff --git i/arch/arm64/boot/dts/arm/morello.dtsi w/arch/arm64/boot/dts/arm/morello.dtsi
index e35e5e482720..0bab0b3ea969 100644
--- i/arch/arm64/boot/dts/arm/morello.dtsi
+++ w/arch/arm64/boot/dts/arm/morello.dtsi
@@ -224,7 +224,7 @@ uart0: serial@2a400000 {
                        status = "disabled";
                };

-               gic: interrupt-controller@2c010000 {
+               gic: interrupt-controller@30000000 {
                        compatible = "arm,gic-v3";
                        reg = <0x0 0x30000000 0x0 0x10000>,     /* GICD */
                              <0x0 0x300c0000 0x0 0x80000>;     /* GICR */
@@ -293,7 +293,7 @@ mailbox: mhu@45000000 {
                        clock-names = "apb_pclk";
                };

-               sram: sram@45200000 {
+               sram: sram@6000000 {
                        compatible = "mmio-sram";
                        reg = <0x0 0x06000000 0x0 0x8000>;
                        ranges = <0 0x0 0x06000000 0x8000>;

Re: (subset) [PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Sudeep Holla]

On Fri, 21 Feb 2025 18:03:39 +0000, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA [1].
> 
> This series adds dts support for the Arm Morello System Development
> Platform.
> 
> [...]

Applied to sudeep.holla/linux (for-next/juno/updates), thanks!

[01/10] arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS
        https://git.kernel.org/sudeep.holla/c/a3b955ac911b
[02/10] dt-bindings: arm: Add Morello compatibility
        https://git.kernel.org/sudeep.holla/c/51e877f12d23
[03/10] dt-bindings: arm: Add Morello fvp compatibility
        https://git.kernel.org/sudeep.holla/c/73d251e7068c
[04/10] dt-bindings: arm: Add Rainier compatibility
        https://git.kernel.org/sudeep.holla/c/91ee16438965
[05/10] dt-bindings: arm-pmu: Add support for ARM Rainier PMU
        https://git.kernel.org/sudeep.holla/c/807945ae7325
[07/10] arm64: dts: morello: Add support for common functionalities
        https://git.kernel.org/sudeep.holla/c/8fc53e26fdd8
[08/10] arm64: dts: morello: Add support for soc dts
        https://git.kernel.org/sudeep.holla/c/7f6838da3c67
[09/10] arm64: dts: morello: Add support for fvp dts
        https://git.kernel.org/sudeep.holla/c/34f3b3745ce5
[10/10] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer
        https://git.kernel.org/sudeep.holla/c/6ceb0dd64727
--
Regards,
Sudeep

Re: [PATCH v7 01/10] arm64: Kconfig: Update description for CONFIG_ARCH_VEXPRESS

[Liviu Dudau]

On Fri, Feb 21, 2025 at 06:03:40PM +0000, Vincenzo Frascino wrote:
> Update the description and contextually the help text of
> CONFIG_ARCH_VEXPRESS to reflect the inclusion of all ARM Ltd Platforms.
> 
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>

Best regards,
Liviu

> ---
>  arch/arm64/Kconfig.platforms | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 02f9248f7c84..c468c23b2bba 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -374,13 +374,12 @@ config ARCH_UNIPHIER
>  	  This enables support for Socionext UniPhier SoC family.
>  
>  config ARCH_VEXPRESS
> -	bool "ARMv8 software model (Versatile Express)"
> +	bool "ARM Ltd Platforms"
>  	select GPIOLIB
>  	select PM
>  	select PM_GENERIC_DOMAINS
>  	help
> -	  This enables support for the ARMv8 software model (Versatile
> -	  Express).
> +	  This enables support for the ARM Ltd Platforms.
>  
>  config ARCH_VISCONTI
>  	bool "Toshiba Visconti SoC Family"
> -- 
> 2.43.0
> 

-- 
====================
| I would like to |
| fix the world,  |
| but they're not |
| giving me the   |
 \ source code!  /
  ---------------
    ¯\_(ツ)_/¯

Re: [PATCH v7 06/10] perf: arm_pmuv3: Add support for ARM Rainier PMU

[Will Deacon]

On Thu, Feb 27, 2025 at 10:10:30AM +0000, Sudeep Holla wrote:
> 
> On Fri, Feb 21, 2025 at 06:03:45PM +0000, Vincenzo Frascino wrote:
> > Add support for the ARM Rainier CPU core PMU.
> >
> 
> I can't take this through Arm SoC as the DTS and dt-bindings changes
> are kept separate from the driver changes in their pull request to Linus.
> 
> I need to keep the bindings(05/10) and the DTS(07/10) together to avoid
> DTC warnings.
> 
> So the 2 options I see are:
> Defer this driver change until the bindings last upstream.
> OR
> Just take the perf driver change without the binding via perf tree
> 
> For now, I will take all other patches except this.

Works for me. I'll pick up the driver patch.

Will

Re: [PATCH v7 06/10] perf: arm_pmuv3: Add support for ARM Rainier PMU

[Sudeep Holla]

On Thu, Feb 27, 2025 at 05:14:57PM +0000, Will Deacon wrote:
> On Thu, Feb 27, 2025 at 10:10:30AM +0000, Sudeep Holla wrote:
> > 
> > On Fri, Feb 21, 2025 at 06:03:45PM +0000, Vincenzo Frascino wrote:
> > > Add support for the ARM Rainier CPU core PMU.
> > >
> > 
> > I can't take this through Arm SoC as the DTS and dt-bindings changes
> > are kept separate from the driver changes in their pull request to Linus.
> > 
> > I need to keep the bindings(05/10) and the DTS(07/10) together to avoid
> > DTC warnings.
> > 
> > So the 2 options I see are:
> > Defer this driver change until the bindings last upstream.
> > OR
> > Just take the perf driver change without the binding via perf tree
> > 
> > For now, I will take all other patches except this.
> 
> Works for me. I'll pick up the driver patch.
> 

Thanks Will.

-- 
Regards,
Sudeep

Re: [PATCH v7 00/10] arm64: dts: Add Arm Morello support

[Will Deacon]

On Fri, 21 Feb 2025 18:03:39 +0000, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA [1].
> 
> This series adds dts support for the Arm Morello System Development
> Platform.
> 
> [...]

Applied PMU driver change to will (for-next/perf), thanks!

[06/10] perf: arm_pmuv3: Add support for ARM Rainier PMU
        https://git.kernel.org/will/c/0424b1a81a42

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev