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Mon, 3 Mar 2025 19:38:52 +0800 (CST) Date: Mon, 3 Mar 2025 19:38:47 +0800 From: Peter Chen To: Marc Zyngier Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, Fugang Duan Subject: Re: [PATCH v3 6/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support Message-ID: References: <20250227120619.1741431-1-peter.chen@cixtech.com> <20250227120619.1741431-7-peter.chen@cixtech.com> <86r03ip0kf.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86r03ip0kf.wl-maz@kernel.org> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66C9:EE_|TYSPR06MB6647:EE_ X-MS-Office365-Filtering-Correlation-Id: 38389ff4-3c56-4d03-e7f7-08dd5a47f9b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2025 11:38:53.3032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38389ff4-3c56-4d03-e7f7-08dd5a47f9b2 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66C9.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6647 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250303_033906_346196_9B07B592 X-CRM114-Status: GOOD ( 23.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 25-02-28 15:10:24, Marc Zyngier wrote: Hi Marc, Thanks for your detail review. > > + > > + cpu10: cpu@a00 { > > + compatible = "arm,cortex-a720"; > > + enable-method = "psci"; > > + reg = <0x0 0xa00>; > > + device_type = "cpu"; > > + capacity-dmips-mhz = <1024>; > > + }; > > + > > + cpu11: cpu@b00 { > > + compatible = "arm,cortex-a720"; > > + enable-method = "psci"; > > + reg = <0x0 0xb00>; > > + device_type = "cpu"; > > + capacity-dmips-mhz = <1024>; > > + }; > > Given that half the A720s are advertised with lower clock speed, how > comes they all have the same capacity? According to Documentation/devicetree/bindings/cpu/cpu-capacity.txt "capacity-dmips-mhz" is u32 value representing CPU capacity expressed in normalized DMIPS/MHz, it means CPU capability per MHz. For sky1 SoC, both middle and big cores are A720, so their capability per MHz are the same. > > + > > + pmu-a520 { > > + compatible = "arm,cortex-a520-pmu"; > > + interrupts = ; > > + }; > > + > > + pmu-a720 { > > + compatible = "arm,cortex-a720-pmu"; > > + interrupts = ; > > + }; > > This is wrong. The default configuration for PPIs is to expose the > *same* device on all CPUs. You must use PPI affinities for your PMUs. > Please see the GICv3 binding for the details. We have discussed internally, we have not seen the benefits routing different PPI interrupt to dedicated CPUs. Any use cases? I prefer changing pmu nodes as one generic Armv8 PMU node. Is it accepted? Or must I keep both pmu for A520 and A720, and add PPI affinities to describe hardware well? > > > + > > + pmu-spe { > > + compatible = "arm,statistical-profiling-extension-v1"; > > + interrupts = ; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + soc@0 { > > + compatible = "simple-bus"; > > + ranges = <0 0 0 0 0x20 0>; > > + dma-ranges; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + gic: interrupt-controller@e010000 { > > + compatible = "arm,gic-v3"; > > + reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ > > + <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ > > + interrupts = ; > > + #interrupt-cells = <3>; > > This will need to be bumped up to 4, and all the interrupt specifiers adjusted. Depends on if PPI affinities is must. > > > + interrupt-controller; > > + #redistributor-regions = <1>; > > Drop this, this is useless. It is pretty obvious that there is a > single RD region, and 1 is the default. > > > + redistributor-stride = <0 0x40000>; > > Drop this. This is a standard GIC700 that doesn't need any help > computing the stride as it obeys the architecture. Will drop above two properties. > > > + #address-cells = <2>; > > + #size-cells = <2>; > > I don't understand why you repeat this on every sub-nodes. Because there is a child node for gic_its below > > > + ranges; > > + > > + gic_its: msi-controller@e050000 { > > + compatible = "arm,gic-v3-its"; > > + reg = <0x0 0x0e050000 0x0 0x30000>; > > + msi-controller; > > + #msi-cells = <1>; > > + }; > > + }; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; > > + interrupts = , > > + , > > + , > > + , > > + ; > > + clock-frequency = <1000000000>; > > Drop this. The firmware already sets CNTFRQ_EL0 to the correct value, > it seems. And if it doesn't, please fix the firmware. Yes, you are right, firmware configures it, I will delete it at next version. > > > + arm,no-tick-in-suspend; > > Why do you need this? Is the HW so broken that you have implemented > the global counter in a power domain that isn't always on? > Not hardware broken, just arch timer will be powered off at cpu idle and system suspend due to power consumption reason. -- Best regards, Peter