[PATCH] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[PATCH] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[Hugues KAMBA MPIANA]

Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
enable support for secondary CPU cores.

This update facilitates symmetric multiprocessing (SMP) support on
the Corstone1000 Fixed Virtual Platform (FVP), allowing the
secondary cores to be properly initialised and utilised.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
---
 arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 24 ++++++++++++++++++++
 arch/arm64/boot/dts/arm/corstone1000.dtsi    |  2 +-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
index abd013562995..df9700302b8d 100644
--- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -49,3 +49,27 @@ sdmmc1: mmc@50000000 {
 		clock-names = "smclk", "apb_pclk";
 	};
 };
+
+&cpus {
+	cpu1: cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a35";
+		reg = <0x1>;
+		enable-method = "psci";
+		next-level-cache = <&L2_0>;
+	};
+	cpu2: cpu@2 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a35";
+		reg = <0x2>;
+		enable-method = "psci";
+		next-level-cache = <&L2_0>;
+	};
+	cpu3: cpu@3 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a35";
+		reg = <0x3>;
+		enable-method = "psci";
+		next-level-cache = <&L2_0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index bb9b96fb5314..b4364c61901c 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -21,7 +21,7 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	cpus {
+	cpus: cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 

Re: [PATCH] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[Sudeep Holla]

On Mon, Mar 03, 2025 at 03:37:44PM +0000, Hugues KAMBA MPIANA wrote:
> Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
> enable support for secondary CPU cores.
> 
> This update facilitates symmetric multiprocessing (SMP) support on
> the Corstone1000 Fixed Virtual Platform (FVP), allowing the
> secondary cores to be properly initialised and utilised.
> 
> Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
> ---
>  arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 24 ++++++++++++++++++++
>  arch/arm64/boot/dts/arm/corstone1000.dtsi    |  2 +-
>  2 files changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> index abd013562995..df9700302b8d 100644
> --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> @@ -49,3 +49,27 @@ sdmmc1: mmc@50000000 {
>  		clock-names = "smclk", "apb_pclk";
>  	};
>  };
> +
> +&cpus {
> +	cpu1: cpu@1 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a35";
> +		reg = <0x1>;
> +		enable-method = "psci";
> +		next-level-cache = <&L2_0>;
> +	};
> +	cpu2: cpu@2 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a35";
> +		reg = <0x2>;
> +		enable-method = "psci";
> +		next-level-cache = <&L2_0>;
> +	};
> +	cpu3: cpu@3 {
> +		device_type = "cpu";
> +		compatible = "arm,cortex-a35";
> +		reg = <0x3>;
> +		enable-method = "psci";
> +		next-level-cache = <&L2_0>;
> +	};

Why are these not part of /cpus node in corstone1000.dtsi ?
Also I see the original cpu@0 node doesn't have enable-method set to
"psci" while these secondary cpus have. Please add the same and move all
these changes in corstone1000.dtsi unless you have strong reasons not to.

In that case, please clearly state the reason in the commit message.

P.S: I was about to send PR soon for v6.15. If you want this change for
v6.15, you need to be quicker.

-- 
Regards,
Sudeep

[PATCH v2] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[Hugues KAMBA MPIANA]

Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
enable support for secondary CPU cores.

This update facilitates symmetric multiprocessing (SMP) support on
the Corstone1000 Fixed Virtual Platform (FVP), allowing the
secondary cores to be properly initialised and utilised.

Only FVP platform will have SMP support and hence the secondary cpu definitions
are not added to corstone1000.dtsi.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
---
 arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 24 ++++++++++++++++++++
 arch/arm64/boot/dts/arm/corstone1000.dtsi    |  2 +-
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
index abd013562995..df9700302b8d 100644
--- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -49,3 +49,27 @@ sdmmc1: mmc@50000000 {
 		clock-names = "smclk", "apb_pclk";
 	};
 };
+
+&cpus {
+	cpu1: cpu@1 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a35";
+		reg = <0x1>;
+		enable-method = "psci";
+		next-level-cache = <&L2_0>;
+	};
+	cpu2: cpu@2 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a35";
+		reg = <0x2>;
+		enable-method = "psci";
+		next-level-cache = <&L2_0>;
+	};
+	cpu3: cpu@3 {
+		device_type = "cpu";
+		compatible = "arm,cortex-a35";
+		reg = <0x3>;
+		enable-method = "psci";
+		next-level-cache = <&L2_0>;
+	};
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index bb9b96fb5314..b4364c61901c 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -21,7 +21,7 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	cpus {
+	cpus: cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 

Re: [PATCH v2] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[Sudeep Holla]

On Mon, 03 Mar 2025 17:00:12 +0000, Hugues KAMBA MPIANA wrote:
> Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
> enable support for secondary CPU cores.
>
> This update facilitates symmetric multiprocessing (SMP) support on
> the Corstone1000 Fixed Virtual Platform (FVP), allowing the
> secondary cores to be properly initialised and utilised.
>
> [...]

Applied to sudeep.holla/linux (for-next/juno/updates), thanks!

[1/1] arm64: dts: corstone1000: Add definitions for secondary CPU cores
      https://git.kernel.org/sudeep.holla/c/21b9f56cec8f
--
Regards,
Sudeep

Re: [PATCH v2] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[Krzysztof Kozlowski]

On 04/03/2025 11:08, Sudeep Holla wrote:
> On Mon, 03 Mar 2025 17:00:12 +0000, Hugues KAMBA MPIANA wrote:
>> Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
>> enable support for secondary CPU cores.
>>
>> This update facilitates symmetric multiprocessing (SMP) support on
>> the Corstone1000 Fixed Virtual Platform (FVP), allowing the
>> secondary cores to be properly initialised and utilised.
>>
>> [...]
> 
> Applied to sudeep.holla/linux (for-next/juno/updates), thanks!
> 
> [1/1] arm64: dts: corstone1000: Add definitions for secondary CPU cores
>       https://git.kernel.org/sudeep.holla/c/21b9f56cec8f

Why? Nothing improved here comparing to v1.

Your comment are still valid and the patch is still not correct.

Best regards,
Krzysztof

Re: [PATCH v2] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[Krzysztof Kozlowski]

On 03/03/2025 18:00, Hugues KAMBA MPIANA wrote:
> Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
> enable support for secondary CPU cores.
> 
> This update facilitates symmetric multiprocessing (SMP) support on
> the Corstone1000 Fixed Virtual Platform (FVP), allowing the
> secondary cores to be properly initialised and utilised.
> 
> Only FVP platform will have SMP support and hence the secondary cpu definitions
> are not added to corstone1000.dtsi.
> 
> Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
> ---
>  arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 24 ++++++++++++++++++++
>  arch/arm64/boot/dts/arm/corstone1000.dtsi    |  2 +-
>  2 files changed, 25 insertions(+), 1 deletion(-)
> 
No, nothing improved.

Provide detailed changelog after the ---.

Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets.

Best regards,
Krzysztof

Re: [PATCH v2] arm64: dts: corstone1000: Add definitions for secondary CPU cores

[Sudeep Holla]

On Tue, Mar 04, 2025 at 11:12:57AM +0100, Krzysztof Kozlowski wrote:
> On 04/03/2025 11:08, Sudeep Holla wrote:
> > On Mon, 03 Mar 2025 17:00:12 +0000, Hugues KAMBA MPIANA wrote:
> >> Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
> >> enable support for secondary CPU cores.
> >>
> >> This update facilitates symmetric multiprocessing (SMP) support on
> >> the Corstone1000 Fixed Virtual Platform (FVP), allowing the
> >> secondary cores to be properly initialised and utilised.
> >>
> >> [...]
> > 
> > Applied to sudeep.holla/linux (for-next/juno/updates), thanks!
> > 
> > [1/1] arm64: dts: corstone1000: Add definitions for secondary CPU cores
> >       https://git.kernel.org/sudeep.holla/c/21b9f56cec8f
> 
> Why? Nothing improved here comparing to v1.
> 
> Your comment are still valid and the patch is still not correct.
> 

It was not marked clearly or noted as change. I agree that is confusing.

However the following was added:

"Only FVP platform will have SMP support and hence the secondary cpu
definitions are not added to corstone1000.dtsi"

Hugues pinged me in private to explain why it is done in that way and I
asked him to add the reasoning in the commit message which he did but
failed to capture in the v1->v2 changelog. I mentioned it in private
again as he is new contributor to the kernel, I was less strict on him 😉.

--
Regards,
Sudeep