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Tue, 4 Mar 2025 21:05:39 +0800 (CST) Date: Tue, 4 Mar 2025 21:05:33 +0800 From: Peter Chen To: Marc Zyngier Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, Fugang Duan Subject: Re: [PATCH v3 6/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support Message-ID: References: <20250227120619.1741431-1-peter.chen@cixtech.com> <20250227120619.1741431-7-peter.chen@cixtech.com> <86r03ip0kf.wl-maz@kernel.org> <86ikoqoso9.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86ikoqoso9.wl-maz@kernel.org> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66D0:EE_|KL1PR06MB6371:EE_ X-MS-Office365-Filtering-Correlation-Id: 69b3775f-4380-4da7-4d43-08dd5b1d43de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2025 13:05:40.5268 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 69b3775f-4380-4da7-4d43-08dd5b1d43de X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66D0.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR06MB6371 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250304_050553_247767_0375CED0 X-CRM114-Status: GOOD ( 27.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 25-03-03 18:49:58, Marc Zyngier wrote: > > > > + > > > > + pmu-a520 { > > > > + compatible = "arm,cortex-a520-pmu"; > > > > + interrupts = ; > > > > + }; > > > > + > > > > + pmu-a720 { > > > > + compatible = "arm,cortex-a720-pmu"; > > > > + interrupts = ; > > > > + }; > > > > > > This is wrong. The default configuration for PPIs is to expose the > > > *same* device on all CPUs. You must use PPI affinities for your PMUs. > > > Please see the GICv3 binding for the details. > > > > We have discussed internally, we have not seen the benefits routing > > different PPI interrupt to dedicated CPUs. Any use cases? > > This isn't about changing the PPI. It is about matching CPUs with > their PMU. Here, you are saying "both PMU types are connected to all > the CPUs using PPI7". > > That's obviously not the case. > > > I prefer changing pmu nodes as one generic Armv8 PMU node. Is it accepted? > > No, that's not acceptable. > > > Or must I keep both pmu for A520 and A720, and add PPI affinities to > > describe hardware well? > > This is an established practice on all big-little systems: each PMU > node has an affinity that indicates which CPUs they are connected > to. For GICv3+, this is carried by the interrupt specifier. > > Please look at existing SoCs supported, such as rk3399, for example. I see. I will add ppi-partitions for gic-v3 node. > > > > > > This will need to be bumped up to 4, and all the interrupt specifiers adjusted. > > > > Depends on if PPI affinities is must. > > Definitely a must, unless you want to completely remove all traces of > the PMU, which is of course silly, but a valid alternative. I will change #interrupt-cells to 4, and applies to all interrupt specifiers. > > > > > + arm,no-tick-in-suspend; > > > > > > Why do you need this? Is the HW so broken that you have implemented > > > the global counter in a power domain that isn't always on? > > > > > > > Not hardware broken, just arch timer will be powered off at cpu idle > > and system suspend due to power consumption reason. > > This is not about the timer. This is about the global counter. If your > counter stops ticking when you're in idle or suspended, your system is > broken and you need this property. If the timer (or more precisely the > comparator) is turned off because the CPU is off, then that's the > expected behaviour and you don't need this property. > I will delete this property. -- Best regards, Peter