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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1ffbcf00sm129988595e9.10.2025.03.18.03.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Mar 2025 03:46:23 -0700 (PDT) Date: Tue, 18 Mar 2025 10:46:18 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: Alim Akhtar , Alyssa Rosenzweig , Albert Ou , asahi@lists.linux.dev, Lu Baolu , David Woodhouse , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Marek Szyprowski , Hector Martin , Palmer Dabbelt , Paul Walmsley , Robin Murphy , Samuel Holland , Suravee Suthikulpanit , Sven Peter , Thierry Reding , Tomasz Jeznach , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Bagas Sanjaya , Joerg Roedel , Pasha Tatashin , patches@lists.linux.dev, David Rientjes , Matthew Wilcox Subject: Re: [PATCH v3 20/23] iommu: Update various drivers to pass in lg2sz instead of order to iommu pages Message-ID: References: <0-v3-e797f4dc6918+93057-iommu_pages_jgg@nvidia.com> <20-v3-e797f4dc6918+93057-iommu_pages_jgg@nvidia.com> <20250317133500.GC9311@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250317133500.GC9311@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_034626_644610_3A0DDDAA X-CRM114-Status: GOOD ( 25.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Mar 17, 2025 at 10:35:00AM -0300, Jason Gunthorpe wrote: > On Wed, Mar 12, 2025 at 12:59:00PM +0000, Mostafa Saleh wrote: > > > --- a/drivers/iommu/io-pgtable-arm.c > > > +++ b/drivers/iommu/io-pgtable-arm.c > > > @@ -263,14 +263,13 @@ static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, > > > void *cookie) > > > { > > > struct device *dev = cfg->iommu_dev; > > > - int order = get_order(size); > > > dma_addr_t dma; > > > void *pages; > > > > > > if (cfg->alloc) > > > pages = cfg->alloc(cookie, size, gfp); > > > else > > > - pages = iommu_alloc_pages_node(dev_to_node(dev), gfp, order); > > > + pages = iommu_alloc_pages_node_sz(dev_to_node(dev), gfp, size); > > > > Although, the current implementation of iommu_alloc_pages_node_sz() would round > > the size to order, but this is not correct according to the API definition > > "The returned allocation is round_up_pow_two(size) big, and is physically aligned > > to its size." > > Yes.. The current implementation is limited to full PAGE_SIZE only, > the documentation imagines a future where it is not. Drivers should > ideally not assume the PAGE_SIZE limit during this conversion. > > > I'd say we can align the size or use min with 64 bytes before calling the > > function would be enough (or change the API to state that allocations > > are rounded to order) > > OK, like this: > > if (cfg->alloc) { > pages = cfg->alloc(cookie, size, gfp); > } else { > /* > * For very small starting-level translation tables the HW > * requires a minimum alignment of at least 64 to cover all > * cases. > */ > pages = iommu_alloc_pages_node_sz(dev_to_node(dev), gfp, > max(size, 64)); > } Yes, that looks good. Thanks, Mostafa > > Thanks, > Jason