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From: Oliver Upton To: David Hildenbrand Cc: Catalin Marinas , Jason Gunthorpe , Marc Zyngier , Ankit Agrawal , "joey.gouly@arm.com" , "suzuki.poulose@arm.com" , "yuzenghui@huawei.com" , "will@kernel.org" , "ryan.roberts@arm.com" , "shahuang@redhat.com" , "lpieralisi@kernel.org" , Aniket Agashe , Neo Jia , Kirti Wankhede , "Tarun Gupta (SW-GPU)" , Vikram Sethi , Andy Currid , Alistair Popple , John Hubbard , Dan Williams , Zhi Wang , Matt Ochs , Uday Dhoke , Dheeraj Nigam , Krishnakant Jaju , "alex.williamson@redhat.com" , "sebastianene@google.com" , "coltonlewis@google.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "ardb@kernel.org" , "akpm@linux-foundation.org" , "gshan@redhat.com" , "linux-mm@kvack.org" , "ddutile@redhat.com" , "tabba@google.com" , "qperret@google.com" , "seanjc@google.com" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags Message-ID: References: <86r033olwv.wl-maz@kernel.org> <87tt7y7j6r.wl-maz@kernel.org> <8634fcnh0n.wl-maz@kernel.org> <86wmcmn0dp.wl-maz@kernel.org> <20250318125527.GP9311@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250318_124105_650530_D776C9DB X-CRM114-Status: GOOD ( 25.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 18, 2025 at 08:35:38PM +0100, David Hildenbrand wrote: > On 18.03.25 20:27, Catalin Marinas wrote: > > On Tue, Mar 18, 2025 at 09:55:27AM -0300, Jason Gunthorpe wrote: > > > On Tue, Mar 18, 2025 at 09:39:30AM +0000, Marc Zyngier wrote: > > > > The memslot must also be created with a new flag ((2c) in the taxonomy > > > > above) that carries the "Please map VM_PFNMAP VMAs as cacheable". This > > > > flag is only allowed if (1) is valid. > > > > > > > > This results in the following behaviours: > > > > > > > > - If the VMM creates the memslot with the cacheable attribute without > > > > (1) being advertised, we fail. > > > > > > > > - If the VMM creates the memslot without the cacheable attribute, we > > > > map as NC, as it is today. > > > > > > Is that OK though? > > > > > > Now we have the MM page tables mapping this memory as cachable but KVM > > > and the guest is accessing it as non-cached. > > > > I don't think we should allow this. > > > > > I thought ARM tried hard to avoid creating such mismatches? This is > > > why the pgprot flags were used to drive this, not an opt-in flag. To > > > prevent userspace from forcing a mismatch. > > > > We have the vma->vm_page_prot when the memslot is added, so we could use > > this instead of additional KVM flags. > > I thought we try to avoid messing with the VMA when adding memslots; because > KVM_CAP_SYNC_MMU allows user space for changing the VMAs afterwards without > changing the memslot? Any checks on the VMA at memslot creation is done out of courtesy to userspace so it 'fails fast'. We repeat checks on the VMA at the time of fault to handle userspace twiddling VMAs behind our back. VM_MTE_ALLOWED is an example of this. Thanks, Oliver