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Thu, 9 Mar 2023 17:54:16 -0800 Date: Thu, 9 Mar 2023 17:54:15 -0800 From: Nicolin Chen To: Shameerali Kolothum Thodi CC: Robin Murphy , "jgg@nvidia.com" , "will@kernel.org" , "eric.auger@redhat.com" , "kevin.tian@intel.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "jean-philippe@linaro.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Message-ID: References: <995e48fe6eb9e31c71dbe8bb80d445aa34a51819.1678348754.git.nicolinc@nvidia.com> <4e426dc4-6852-336f-7321-5b4df69fd430@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT022:EE_|IA0PR12MB8328:EE_ X-MS-Office365-Filtering-Correlation-Id: b0966e49-cb1a-47d2-dd9c-08db210a6474 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 09, 2023 at 06:24:29PM +0000, Shameerali Kolothum Thodi wrote: > External email: Use caution opening links or attachments > > > > -----Original Message----- > > From: Robin Murphy [mailto:robin.murphy@arm.com] > > Sent: 09 March 2023 13:13 > > To: Nicolin Chen ; jgg@nvidia.com; will@kernel.org > > Cc: eric.auger@redhat.com; kevin.tian@intel.com; baolu.lu@linux.intel.com; > > joro@8bytes.org; Shameerali Kolothum Thodi > > ; jean-philippe@linaro.org; > > linux-arm-kernel@lists.infradead.org; iommu@lists.linux.dev; > > linux-kernel@vger.kernel.org > > Subject: Re: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding > > STE fields when s2_cfg is NULL > > > > On 2023-03-09 10:53, Nicolin Chen wrote: > > > From: Eric Auger > > > > > > Despite the spec does not seem to mention this, on some implementations, > > > when the STE configuration switches from an S1+S2 cfg to an S1 only one, > > > a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset. > > > > Can you provide more details, since it's not clear whether this is a > > hardware erratum workaround or a bodge around the driver itself doing > > something wrong like not doing a proper break-before-make transition of > > the STE. The architecture explicitly states that all the STE.S2* fields > > except S2VMID and potentially S2S are ignored when Stage 2 is bypassed. > > Took a while to locate the email thread where this was discussed, > https://patchwork.kernel.org/cover/11449895/#23244457 > > This was observed on a HiSilicon implementation where, if the SMMUv3 is configured with > both Stage 1 and Stage 2 (nested) mode once, then it is not possible to configure it back > for Stage 1 mode for the same device(stream id). > > IIRC, the SMMUv3 implementation on these boards expects to set the S2TTB field in STE to zero > when using S1, otherwise it reports C_BAD_STE error. :( > > You are right that the specification doesn't demand this and I am not sure there are any other > Hardware that requires this. > > Could we please have this with a comment added in the code? Yes, I can add that, and put that link in the commit message too. Thanks Nicolin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel