RE: [PATCH v1 02/14] iommufd: Add nesting related data structures for ARM SMMUv3

Tian, Kevin
2023-03-17T10:11:32Z

> From: Jason Gunthorpe <jgg@nvidia.com>
> Sent: Saturday, March 11, 2023 12:03 AM
>
> On Fri, Mar 10, 2023 at 03:57:27PM +0000, Robin Murphy wrote:
>
> > about the nitty-gritty of all the IOMMU-specific moving parts around it. For
> > guests that want to get into more advanced stuff like managing their own
> > PASID tables, pushing them towards "native" nesting probably does make
> more
> > sense.
>
> IMHO with the simplified virtio model I would say the guest should
> not have its own PASID table.
>
> hyper trap to install a PASID and let the hypervisor driver handle
> this abstractly. If abstractly is the whole point and benifit then
> virtio should lean into that.
>
> This also means virtio protocol doesn't do PASID invalidation. It
> invalidates an ASID and the hypervisor takes care of whatever it is
> connected to. Very simple and general for the VM.

this sounds fair, if ASID here refers a general ID identifying the page
table instead of ARM specific ASID. 😊

but guest still needs to manage the PASID and program PASID into
the assigned device to tag DMA.

>
> Adding a S1 iommu_domain op for invalidate address range is perfectly
> fine and the virtio kernel hypervisor driver can call it generically.
>
> The primary reason to have guest-owned PASID tables is CC stuff, which
> definitely won't be part of virtio-iommu.
>

This fits Intel well.