From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79F6EC76196 for ; Thu, 6 Apr 2023 16:57:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=95xX8rjjCsX2TsF+bgimuqsBg+Jjfk4KDwUQjpej9CA=; b=t2ZBnjqRkdsa/W K3m0V2x524fA3y5WjxCT7GJbz5Mj98nDbHfV4wWAN8u2GSQDTBasjw8zUDSSZAMkTiZ3mjwFX2ZXr DWpH9gFv03O21aEME/XsMEQNnRq1itaQMI1XjM4rX11lPJxhSL9QRgmo+6Ma+A9TwwJKI8fU7mF7D Lb8squcQKMNj6qjWaV+fvw7ccaE6nSrTGmI4jajhznPaBS+m2AiBfGLsm6/XXqQBCsxcEWXaK7Zjq WbL/hGzWIzfnvPdWvV7IBjeGN3i+dKbFyypNDtDiIu4DmZTW8oclO65owqRWvMCtAdHRSzzsUPp38 iBqfm2XNEX1i1Nsrg8SA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pkSuh-00848U-2P; Thu, 06 Apr 2023 16:56:43 +0000 Received: from out-28.mta1.migadu.com ([2001:41d0:203:375::1c]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pkSue-00846a-04 for linux-arm-kernel@lists.infradead.org; Thu, 06 Apr 2023 16:56:42 +0000 Date: Thu, 6 Apr 2023 16:56:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1680800196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=hWGOnY/KsMmqLwQwCb4u5bdX0ysrjDAt55lAt16ploc=; b=NkEI1OIm2rU+3hnzMAsNu8DP68SPnZe0M2ge3UVbzLNf1YONeH1Gi8YIQLAloNq3dSiNlY ffsdK8Z+2FqZ8aeK5SPUHLcgJGXlXWPdDURaPVXEphxj5lPLstWvPVXSs3pKOYa+VPRwQN LJKwv5rO9zKBmeN5t4cCCkAEV8t10QU= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Suzuki K Poulose , Zenghui Yu , Will Deacon Subject: Re: [PATCH 1/2] KVM: arm64: nvhe: Synchronise with page table walker on MMU update Message-ID: References: <20230330100419.1436629-1-maz@kernel.org> <20230330100419.1436629-2-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230330100419.1436629-2-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230406_095641_196784_394576AB X-CRM114-Status: GOOD ( 15.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hey Marc, On Thu, Mar 30, 2023 at 11:04:18AM +0100, Marc Zyngier wrote: > When taking an exception between the EL1&0 translation regime and > the EL2 translation regime, the page table walker is allowed to > complete the walks started from EL0 or EL1 while running at EL2. > > It means that altering the system registers that define the EL1&0 > translation regime is fraught with danger *unless* we wait for > the completion of such walk with a DSB (R_LFHQG and subsequent > statements in the ARM ARM). We already did the right thing for > other external agents (SPE, TRBE), but not the PTW. > > In the case of nVHE, this is a bit involved, as there are a number > of situations where this can happen (such as switching between > host and guest, invalidating TLBs...). I'm assuming that the dsb(ishst) done in some of the other TLB invalidation handlers is sufficient, as R_LFHQG does not describe the scope of the DSB (i.e. loads and/or stores). Nonetheless, short of any special serialization rules, it seems probable for the PTW to have both outstanding loads and stores. Is there some other language in the architecture that speaks to the effects of _any_ DSB on the PTW? I couldn't find it myself. In any case, I'll have to take you at your word if you say it is sufficient :) -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel