From: Catalin Marinas <catalin.marinas@arm.com>
To: Joey Gouly <joey.gouly@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, nd@arm.com,
broonie@kernel.org, james.morse@arm.com, mark.rutland@arm.com,
maz@kernel.org, oliver.upton@linux.dev, suzuki.poulose@arm.com,
will@kernel.org, yuzenghui@huawei.com
Subject: Re: [PATCH v1 16/18] arm64: add encodings of PIRx_ELx registers
Date: Mon, 27 Mar 2023 18:07:24 +0100 [thread overview]
Message-ID: <ZCHNTMa694dl/RDS@arm.com> (raw)
In-Reply-To: <20230309145246.22787-17-joey.gouly@arm.com>
On Thu, Mar 09, 2023 at 02:52:44PM +0000, Joey Gouly wrote:
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index f658aafc47df..11c81e700335 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -170,6 +170,14 @@
> #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
> #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
>
> +/*
> + * PIIndex[3:0] encoding (Permission Indirection Extension)
> + */
> +#define PTE_PI_IDX_0 6
> +#define PTE_PI_IDX_1 51
> +#define PTE_PI_IDX_2 53
> +#define PTE_PI_IDX_3 54
> +
> /*
> * Memory Attribute override for Stage-2 (MemAttr[3:0])
> */
> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> index a45af0a22b25..2b192da1ef9d 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -107,4 +107,22 @@ extern bool arm64_use_ng_mappings;
>
> #endif /* __ASSEMBLY__ */
>
> +#define PIE_E0 ( \
> + PIRx_ELx_PERMIDX(PIE_X_O, pte_pi_index(_PAGE_EXECONLY)) | \
> + PIRx_ELx_PERMIDX(PIE_RX, pte_pi_index(_PAGE_READONLY_EXEC)) | \
> + PIRx_ELx_PERMIDX(PIE_RWX, pte_pi_index(_PAGE_SHARED_EXEC)) | \
> + PIRx_ELx_PERMIDX(PIE_R, pte_pi_index(_PAGE_READONLY)) | \
> + PIRx_ELx_PERMIDX(PIE_RW, pte_pi_index(_PAGE_SHARED)))
> +
> +#define PIE_E1 ( \
> + PIRx_ELx_PERMIDX(PIE_NONE_O, pte_pi_index(_PAGE_EXECONLY)) | \
> + PIRx_ELx_PERMIDX(PIE_R, pte_pi_index(_PAGE_READONLY_EXEC)) | \
> + PIRx_ELx_PERMIDX(PIE_RW, pte_pi_index(_PAGE_SHARED_EXEC)) | \
> + PIRx_ELx_PERMIDX(PIE_R, pte_pi_index(_PAGE_READONLY)) | \
> + PIRx_ELx_PERMIDX(PIE_RW, pte_pi_index(_PAGE_SHARED)) | \
> + PIRx_ELx_PERMIDX(PIE_RX, pte_pi_index(_PAGE_KERNEL_ROX)) | \
> + PIRx_ELx_PERMIDX(PIE_RWX, pte_pi_index(_PAGE_KERNEL_EXEC)) | \
> + PIRx_ELx_PERMIDX(PIE_R, pte_pi_index(_PAGE_KERNEL_RO)) | \
> + PIRx_ELx_PERMIDX(PIE_RW, pte_pi_index(_PAGE_KERNEL)))
> +
> #endif /* __ASM_PGTABLE_PROT_H */
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index b6ba466e2e8a..b31d39f22803 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -26,6 +26,12 @@
>
> #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
>
> +#define pte_pi_index(pte) ( \
> + ((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | \
> + ((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | \
> + ((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | \
> + ((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))
You might as well keep this macro with the PIE_E0/E1 definitions above.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
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next prev parent reply other threads:[~2023-03-27 17:08 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 14:52 [PATCH v1 00/18] Permission Indirection Extension Joey Gouly
2023-03-09 14:52 ` [PATCH v1 01/18] arm64/sysreg: Add ID register ID_AA64MMFR3 Joey Gouly
2023-03-09 15:06 ` Mark Brown
2023-03-09 14:52 ` [PATCH v1 02/18] arm64/sysreg: add system registers TCR2_ELx Joey Gouly
2023-03-09 15:16 ` Mark Brown
2023-03-09 14:52 ` [PATCH v1 03/18] arm64/sysreg: add TCR2En to HCRX_EL2 Joey Gouly
2023-03-09 15:23 ` Mark Brown
2023-03-09 14:52 ` [PATCH v1 04/18] arm64/sysreg: add HFGxTR_EL2 bits for Permission Indirection Extension Joey Gouly
2023-03-09 15:25 ` Mark Brown
2023-03-09 14:52 ` [PATCH v1 05/18] arm64/sysreg: add PIR*_ELx registers Joey Gouly
2023-03-09 15:35 ` Mark Brown
2023-03-16 17:23 ` Mark Brown
2023-03-27 12:22 ` Catalin Marinas
2023-04-11 12:48 ` Mark Brown
2023-03-09 14:52 ` [PATCH v1 06/18] arm64: cpufeature: add system register ID_AA64MMFR3 Joey Gouly
2023-03-27 12:23 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 07/18] arm64: cpufeature: add TCR2 cpucap Joey Gouly
2023-03-27 12:58 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 08/18] arm64: cpufeature: add Permission Indirection Extension cpucap Joey Gouly
2023-03-27 13:07 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 09/18] KVM: arm64: Save/restore TCR2_EL1 Joey Gouly
2023-03-27 13:19 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 10/18] KVM: arm64: Save/restore PIE registers Joey Gouly
2023-03-27 13:20 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 11/18] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests Joey Gouly
2023-03-09 16:07 ` Mark Brown
2023-03-09 16:24 ` Marc Zyngier
2023-03-09 17:04 ` Mark Brown
2023-03-10 12:29 ` Marc Zyngier
2023-03-09 16:34 ` Mark Brown
2023-03-09 14:52 ` [PATCH v1 12/18] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS Joey Gouly
2023-03-27 16:44 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 13/18] arm64: add PTE_WRITE to PROT_SECT_NORMAL Joey Gouly
2023-03-27 16:47 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 14/18] arm64: reorganise PAGE_/PROT_ macros Joey Gouly
2023-03-27 16:51 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 15/18] arm64: disable EL2 traps for PIE Joey Gouly
2023-03-09 15:50 ` Mark Brown
2023-03-09 16:27 ` Suzuki K Poulose
2023-03-09 16:38 ` Mark Brown
2023-03-27 16:59 ` Catalin Marinas
2023-03-28 10:34 ` Joey Gouly
2023-03-31 15:15 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 16/18] arm64: add encodings of PIRx_ELx registers Joey Gouly
2023-03-27 17:07 ` Catalin Marinas [this message]
2023-03-09 14:52 ` [PATCH v1 17/18] arm64: enable Permission Indirection Extension (PIE) Joey Gouly
2023-03-27 17:07 ` Catalin Marinas
2023-03-09 14:52 ` [PATCH v1 18/18] arm64: transfer permission indirection settings to EL2 Joey Gouly
2023-03-27 17:08 ` Catalin Marinas
2023-03-17 16:49 ` [PATCH v1 00/18] Permission Indirection Extension Mark Brown
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