From: Mark Rutland <mark.rutland@arm.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: "Ivan T. Ivanov" <iivanov@suse.de>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mark Brown <broonie@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Dong Aisheng <aisheng.dong@nxp.com>,
linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com
Subject: Re: [PATCH] arm64: errata: Add NXP iMX8QM workaround for A53 Cache coherency issue
Date: Mon, 17 Apr 2023 16:35:12 +0100 [thread overview]
Message-ID: <ZD1nMIup6Dk0Re18@FVFF77S0Q05N> (raw)
In-Reply-To: <8890bcc1-b881-e418-40a5-1b5d6cc8757e@arm.com>
On Fri, Apr 14, 2023 at 12:36:53PM +0100, Robin Murphy wrote:
> On 2023-04-13 12:19, Mark Rutland wrote:
> [...]
> > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> > > index 6bf013fb110d..1ed648f7f29a 100644
> > > --- a/arch/arm64/include/asm/cpufeature.h
> > > +++ b/arch/arm64/include/asm/cpufeature.h
> > > @@ -835,7 +835,8 @@ static inline bool system_supports_bti(void)
> > > static inline bool system_supports_tlb_range(void)
> > > {
> > > return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&
> > > - cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
> > > + cpus_have_const_cap(ARM64_HAS_TLB_RANGE) &&
> > > + !cpus_have_const_cap(ARM64_WORKAROUND_NXP_ERR050104);
> > > }
> >
> > It'd be better to handle this in the detection of ARM64_HAS_TLB_RANGE, as we
> > have for CNP where has_useable_cnp() checks for ARM64_WORKAROUND_NVIDIA_CARMEL_CNP.
>
> It's not needed in either place, since neither Cortex-A53 or Cortex-A72
> support FEAT_TLBIRANGE, so this could never be true on affected platforms
> anyway.
Ah, even better -- we can just drop it.
> Tangentially, I understand this platform has an SMMU[1], so I'd say it would
> also be worth checking what SMMU_IDR0.BTM reports. With any luck it might be
> 0, but if it's 1 then strictly it would want to be overridden as part of a
> complete workaround as well. That wouldn't be a practical issue right now,
> not least since the current Linux driver doesn't even use BTM, but it's
> something which could need to be borne in mind in future.
Absolutely.
Mark.
>
> Robin.
>
> [1] https://lore.kernel.org/linux-arm-kernel/20210807104517.24066-1-peng.fan@oss.nxp.com/
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next prev parent reply other threads:[~2023-04-17 15:36 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-12 12:55 [PATCH] arm64: errata: Add NXP iMX8QM workaround for A53 Cache coherency issue Ivan T. Ivanov
2023-04-13 11:19 ` Mark Rutland
2023-04-14 11:36 ` Robin Murphy
2023-04-17 15:35 ` Mark Rutland [this message]
2023-04-18 16:54 ` Ivan T. Ivanov
2023-04-20 17:02 ` Robin Murphy
2023-04-18 13:25 ` Ivan T. Ivanov
2023-04-17 3:07 ` Peng Fan
2023-04-17 14:48 ` Frank Li
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