From: Abel Vesa <abel.vesa@linaro.org>
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>,
Jacky Bai <ping.bai@nxp.com>, Ye Li <ye.li@nxp.com>
Subject: Re: [PATCH 1/5] clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents
Date: Sun, 9 Apr 2023 17:09:27 +0300 [thread overview]
Message-ID: <ZDLHF6VP232yKsCx@linaro.org> (raw)
In-Reply-To: <20230331063814.2462059-2-peng.fan@oss.nxp.com>
On 23-03-31 14:38:10, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> XBAR_DIVBUS and AD_SLOW should set parent to XBAR_AD_DIVPLAT and
> XBAR_DIVBUS respectively, not the NIC_AD. otherwise we will get
> wrong clock rate.
>
> Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp")
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
> ---
> drivers/clk/imx/clk-imx8ulp.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-imx8ulp.c b/drivers/clk/imx/clk-imx8ulp.c
> index a07df3b44703..89121037a8f0 100644
> --- a/drivers/clk/imx/clk-imx8ulp.c
> +++ b/drivers/clk/imx/clk-imx8ulp.c
> @@ -200,8 +200,8 @@ static int imx8ulp_clk_cgc1_init(struct platform_device *pdev)
> clks[IMX8ULP_CLK_NIC_AD_DIVPLAT] = imx_clk_hw_divider_flags("nic_ad_divplat", "nic_sel", base + 0x34, 21, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> clks[IMX8ULP_CLK_NIC_PER_DIVPLAT] = imx_clk_hw_divider_flags("nic_per_divplat", "nic_ad_divplat", base + 0x34, 14, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> clks[IMX8ULP_CLK_XBAR_AD_DIVPLAT] = imx_clk_hw_divider_flags("xbar_ad_divplat", "nic_ad_divplat", base + 0x38, 14, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> - clks[IMX8ULP_CLK_XBAR_DIVBUS] = imx_clk_hw_divider_flags("xbar_divbus", "nic_ad_divplat", base + 0x38, 7, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> - clks[IMX8ULP_CLK_XBAR_AD_SLOW] = imx_clk_hw_divider_flags("xbar_ad_slow", "nic_ad_divplat", base + 0x38, 0, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> + clks[IMX8ULP_CLK_XBAR_DIVBUS] = imx_clk_hw_divider_flags("xbar_divbus", "xbar_ad_divplat", base + 0x38, 7, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
> + clks[IMX8ULP_CLK_XBAR_AD_SLOW] = imx_clk_hw_divider_flags("xbar_ad_slow", "xbar_divbus", base + 0x38, 0, 6, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
>
> clks[IMX8ULP_CLK_SOSC_DIV1_GATE] = imx_clk_hw_gate_dis("sosc_div1_gate", "sosc", base + 0x108, 7);
> clks[IMX8ULP_CLK_SOSC_DIV2_GATE] = imx_clk_hw_gate_dis("sosc_div2_gate", "sosc", base + 0x108, 15);
> --
> 2.37.1
>
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next prev parent reply other threads:[~2023-04-09 14:10 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-31 6:38 [PATCH 0/5] clk: imx: imx8ulp: clk fix and update Peng Fan (OSS)
2023-03-31 6:38 ` [PATCH 1/5] clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents Peng Fan (OSS)
2023-04-09 14:09 ` Abel Vesa [this message]
2023-03-31 6:38 ` [PATCH 2/5] clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate Peng Fan (OSS)
2023-04-09 14:09 ` Abel Vesa
2023-03-31 6:38 ` [PATCH 3/5] clk: imx: imx8ulp: keep MU0_B clock enabled always Peng Fan (OSS)
2023-04-09 14:09 ` Abel Vesa
2023-03-31 6:38 ` [PATCH 4/5] clk: imx: imx8ulp: Add tpm5 clock as critical gate clock Peng Fan (OSS)
2023-04-09 14:10 ` Abel Vesa
2023-03-31 6:38 ` [PATCH 5/5] clk: imx: imx8ulp: update clk flag for system critical clock Peng Fan (OSS)
2023-04-09 14:09 ` Abel Vesa
2023-04-09 14:23 ` [PATCH 0/5] clk: imx: imx8ulp: clk fix and update Abel Vesa
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