Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup

From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Paul Menzel" <pmenzel@molgen.mpg.de>,
	linux-kernel@vger.kernel.org, x86@kernel.org,
	"David Woodhouse" <dwmw2@infradead.org>,
	"Brian Gerst" <brgerst@gmail.com>,
	"Arjan van de Veen" <arjan@linux.intel.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Paul McKenney" <paulmck@kernel.org>,
	"Tom Lendacky" <thomas.lendacky@amd.com>,
	"Oleksandr Natalenko" <oleksandr@natalenko.name>,
	"Guilherme G. Piccoli" <gpiccoli@igalia.com>,
	"Piotr Gorski" <lucjan.lucjanov@gmail.com>,
	"David Woodhouse" <dwmw@amazon.co.uk>,
	"Usama Arif" <usama.arif@bytedance.com>,
	"Jürgen Groß" <jgross@suse.com>,
	"Boris Ostrovsky" <boris.ostrovsky@oracle.com>,
	xen-devel@lists.xenproject.org,
	"Russell King" <linux@armlinux.org.uk>,
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	"Will Deacon" <will@kernel.org>, "Guo Ren" <guoren@kernel.org>,
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	"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
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	"James E. J. Bottomley" <James.Bottomley@hansenpartnership.com>,
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	"Mark Rutland" <mark.rutland@arm.com>,
	"Sabin Rapan" <sabrapan@amazon.com>
Subject: Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup
Date: Thu, 20 Apr 2023 07:51:49 -0700	[thread overview]
Message-ID: <ZEFRhXua6Jxvit1R@google.com> (raw)
In-Reply-To: <87y1mm3iqz.ffs@tglx>

On Thu, Apr 20, 2023, Thomas Gleixner wrote:
> On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote:
> > On 20/04/2023 9:32 am, Thomas Gleixner wrote:
> > > On Wed, Apr 19, 2023, Andrew Cooper wrote:
> > > > This was changed in x2APIC, which made the x2APIC_ID immutable.
>
> >> I'm pondering to simply deny parallel mode if x2APIC is not there.
> >
> > I'm not sure if that will help much.
> 
> Spoilsport.

LOL, well let me pile on then.  x2APIC IDs aren't immutable on AMD hardware.  The
ID is read-only when the CPU is in x2APIC mode, but any changes made to the ID
while the CPU is in xAPIC mode survive the transition to x2APIC.  From the APM:

  A value previously written by software to the 8-bit APIC_ID register (MMIO offset
  30h) is converted by hardware into the appropriate format and reflected into the
  32-bit x2APIC_ID register (MSR 802h).

FWIW, my observations from testing on bare metal are that the xAPIC ID is effectively
read-only (writes are dropped) on Intel CPUs as far back as Haswell, while the above
behavior described in the APM holds true on at least Rome and Milan.

My guess is that Intel's uArch specific behavior of the xAPIC ID being read-only
was introduced when x2APIC came along, but I didn't test farther back than Haswell.

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