From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 95F53C77B76 for ; Thu, 20 Apr 2023 14:52:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=4/6y+bGi+PTxMntg3si2OPAeCbzhkZddVHhmDKBL0XQ=; b=bfnTwtsUAGsiNB498WmdojsCgK e6ursxNBUWST8sEpTABicbL5fnNSipKs2SCR8AY0fATc2jQ50VrvUQ4W9FbZrpShGCJjPJTrF5GrH CUscwmEMRf1+toGJVZNJUcyFTBnG5C5hAN3erQPQHCMxUOY44J6/zkiTTaIaj20ds+0cViTyZT6p7 Xbq/1RzniKNpGAak4cxENaEWXTMhPbgBqgo1MQieUsPPm04Fxg8b42o1DQSBDS33tFpSYGjGnSGgn yX6yFhaeW9kXeqcWGAqoUmO3E1pdKCdz/5MDczb+Bee55G1SCTldzuFCAWX1MqWcCY/6yfSHcHJWn rZTGj0PA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1ppVdc-008LdO-2J; Thu, 20 Apr 2023 14:51:56 +0000 Received: from mail-pg1-x549.google.com ([2607:f8b0:4864:20::549]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1ppVdZ-008Lbz-03 for linux-arm-kernel@lists.infradead.org; Thu, 20 Apr 2023 14:51:54 +0000 Received: by mail-pg1-x549.google.com with SMTP id 41be03b00d2f7-51b121871ecso640064a12.3 for ; Thu, 20 Apr 2023 07:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1682002311; x=1684594311; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=cenhvMgRBJVEyO+DQ1Yk7EeAnoD+Mx3QDGrPvs6dp/U=; b=ozdQf66WPw8ShRBluz+LMQljss+d3T0PBYjA3jmNDdv//pVrmGXx6L9uusb7fIhJSL LymgWp9X3FbkLAAxceftLeQZn0/6M8JdZmIbsV9oONQVhJAe+e9OODUteXA7bMLvWkmz 5ayRkEY6NENxUYGlnGZFkZBlmyRHMXNIOgoLHCbFX3aaDwjuintlWNx5LkJKfs2Sd6PE Ya8JLH6D3Xz61J6mffVksjDGSWXvO9yhMWIRSY/rzCnaTg7svns1MKliwXodcMA+7eb1 u30LO7+8+pIMTa1eXTgGdK8wfjlZ/7y7DufflgYGy0ae6b3znNofgHpeyL7dnXNOKs4z yrGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682002311; x=1684594311; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=cenhvMgRBJVEyO+DQ1Yk7EeAnoD+Mx3QDGrPvs6dp/U=; b=Y/sgMKtF1z4UOMPQxM8lpldzcEEYM4BZ73mPuCZ0e5xzwApY7pdYs1lLS5I2jkxMNx AyI+JGd2+1hIPA0BxPlYkeDlYttfzyaH8EoYsCQmEW36CziBxtSKN1J/zLHmBh7ae2xU Ah8pO2bNyn/VdlYugH4izGPRPprwnM6BV1OquxelV6kvN+V/QEtroGFhQosdQ9wV91He QTDpizJG2pZj9JO4ExcS8flpLxhQIXdHzvIS0cXamBxgNUWksjpDCUuKWvqDqcWLaZQR PSnKsHlAxZtEFWu95b+AyOTTkQxSmxcJQOb6/VEKh6rLDgCFkYtTRGPRjDg4BPQfYyWo 3xow== X-Gm-Message-State: AAQBX9euXqCTNDT1q3QThjv/ZkTUZcIKYF4Pnb6ht2lbzHJj6AnMsH3q lBXSLQcTGWSKeimJxzK7TrihFFV34LE= X-Google-Smtp-Source: AKy350YZDYx9Ka0U+LJTenQgM1KG3UW2Yutu07LdZ7q6GZTzBdJRqMrlgBJSIie+uzUyI4FO9iSrYEblhR4= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:f807:b0:1a6:3a2e:b731 with SMTP id ix7-20020a170902f80700b001a63a2eb731mr623230plb.1.1682002311424; Thu, 20 Apr 2023 07:51:51 -0700 (PDT) Date: Thu, 20 Apr 2023 07:51:49 -0700 In-Reply-To: <87y1mm3iqz.ffs@tglx> Mime-Version: 1.0 References: <87r0sh4m7a.ffs@tglx> <8592a301-9933-1cad-bd61-8d97e7c7493b@molgen.mpg.de> <87a5z443g2.ffs@tglx> <877cu83v45.ffs@tglx> <874jpc3s3r.ffs@tglx> <0f5463fd-9c4a-6361-adbb-dd89dbb9138d@citrix.com> <871qkf3qek.ffs@tglx> <26d385da-2ede-5d73-2959-84c8f7d89e03@citrix.com> <87y1mm3iqz.ffs@tglx> Message-ID: Subject: Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup From: Sean Christopherson To: Thomas Gleixner Cc: Andrew Cooper , Paul Menzel , linux-kernel@vger.kernel.org, x86@kernel.org, David Woodhouse , Brian Gerst , Arjan van de Veen , Paolo Bonzini , Paul McKenney , Tom Lendacky , Oleksandr Natalenko , "Guilherme G. Piccoli" , Piotr Gorski , David Woodhouse , Usama Arif , "=?iso-8859-1?Q?J=FCrgen_Gro=DF?=" , Boris Ostrovsky , xen-devel@lists.xenproject.org, Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Guo Ren , linux-csky@vger.kernel.org, Thomas Bogendoerfer , linux-mips@vger.kernel.org, "James E. J. Bottomley" , Helge Deller , linux-parisc@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, Mark Rutland , Sabin Rapan X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230420_075153_082554_E08254C2 X-CRM114-Status: GOOD ( 17.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 20, 2023, Thomas Gleixner wrote: > On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote: > > On 20/04/2023 9:32 am, Thomas Gleixner wrote: > > > On Wed, Apr 19, 2023, Andrew Cooper wrote: > > > > This was changed in x2APIC, which made the x2APIC_ID immutable. > > >> I'm pondering to simply deny parallel mode if x2APIC is not there. > > > > I'm not sure if that will help much. > > Spoilsport. LOL, well let me pile on then. x2APIC IDs aren't immutable on AMD hardware. The ID is read-only when the CPU is in x2APIC mode, but any changes made to the ID while the CPU is in xAPIC mode survive the transition to x2APIC. From the APM: A value previously written by software to the 8-bit APIC_ID register (MMIO offset 30h) is converted by hardware into the appropriate format and reflected into the 32-bit x2APIC_ID register (MSR 802h). FWIW, my observations from testing on bare metal are that the xAPIC ID is effectively read-only (writes are dropped) on Intel CPUs as far back as Haswell, while the above behavior described in the APM holds true on at least Rome and Milan. My guess is that Intel's uArch specific behavior of the xAPIC ID being read-only was introduced when x2APIC came along, but I didn't test farther back than Haswell. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel