Re: [PATCH 2/4] iommu/arm-smmu-v3: Document MMU-700 erratum 2812531

From: Nicolin Chen <nicolinc@nvidia.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: <will@kernel.org>, <joro@8bytes.org>, <iommu@lists.linux.dev>,
	<linux-arm-kernel@lists.infradead.org>,
	<jean-philippe@linaro.org>
Subject: Re: [PATCH 2/4] iommu/arm-smmu-v3: Document MMU-700 erratum 2812531
Date: Mon, 15 May 2023 08:44:05 -0700	[thread overview]
Message-ID: <ZGJTRc+LYFFX9Sw0@Asurada-Nvidia> (raw)
In-Reply-To: <a45be5e3-c605-f93a-f523-1bb1f6150986@arm.com>

On Fri, May 12, 2023 at 08:23:54PM +0100, Robin Murphy wrote:

> On 2023-05-10 19:31, Nicolin Chen wrote:
> > On Wed, May 10, 2023 at 11:12:05AM -0700, Nicolin Chen wrote:
> > > On Wed, May 10, 2023 at 04:38:44PM +0100, Robin Murphy wrote:
> > > 
> > > > To work around MMU-700 erratum 2812531 we need to ensure that certain
> > > > sequences of commands cannot be issued without an intervening sync. In
> > > > practice this falls out of our current command-batching machinery
> > > > anyway - each batch only contains a single type of invalidation command,
> > > 
> > > Hmm. This doesn't apply to the user cache invalidation solution
> > > in my v2. A user cmdq could possibly mix different commands in
> > > a single batch if the driver isn't aware of such an errata. So,
> > > I think I'd need some twist when the host has a FORCE_SYNC flag
> > > in my v3.
> > 
> > Just found that you unset the NESTING feature flag in PATCH-4
> > for this errata too. So, the solution in my v2 should be safe.
> 
> For the short term at least - we will still need to come up with a more
> practical active mitigation sooner rather than later, since I imagine
> people are likely to be a bit miffed if nesting support lands in distros
> but still refuses to play at all on the newest shiniest hardware.
> Unfortunately all current versions of MMU-700 are affected (hence the
> unconditional nature of this patch), and some of those are going to
> found in production SoCs.

Okay. I will try adding a WAR function following the doc:

1. A Stage 1 Invalidation that is followed by a Stage 2 invalidation
2. A Configuration Invalidation that is followed by any TLB Invalidation
3. A Leaf invalidation that is followed by a Non-leaf invalidation

We don't need anything for (1) as a user CMDQ only has stage-1
invalidations. Adding a SYNC after every CFIG_CD(_ALL) should
work for (2). Then for (3), need to check the leaf bit between
two adjacent NH_VA/NH_VAA commands.

Thanks
Nic

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