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From: Oliver Upton To: Marc Zyngier Cc: Cornelia Huck , Shameerali Kolothum Thodi , Jing Zhang , KVM , KVMARM , ARMLinux , Oliver Upton , Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta Subject: Re: [PATCH v8 0/6] Support writable CPU ID registers from userspace Message-ID: References: <20230503171618.2020461-1-jingzhangos@google.com> <2ef9208dabe44f5db445a1061a0d5918@huawei.com> <868rdomtfo.wl-maz@kernel.org> <1a96a72e87684e2fb3f8c77e32516d04@huawei.com> <87cz30h4nx.fsf@redhat.com> <867ct8mnel.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <867ct8mnel.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230516_093141_815784_251BB3B7 X-CRM114-Status: GOOD ( 24.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 16, 2023 at 02:11:30PM +0100, Marc Zyngier wrote: > On Tue, 16 May 2023 12:55:14 +0100, > Cornelia Huck wrote: > > > > Do you have more concrete ideas for QEMU CPU models already? Asking > > because I wanted to talk about this at KVM Forum, so collecting what > > others would like to do seems like a good idea :) > > I'm not being asked, but I'll share my thoughts anyway! ;-) > > I don't think CPU models are necessarily the most important thing. > Specially when you look at the diversity of the ecosystem (and even > the same CPU can be configured in different ways at integration > time). Case in point, Neoverse N1 which can have its I/D caches made > coherent or not. And the guest really wants to know which one it is > (you can only lie in one direction). > > But being able to control the feature set exposed to the guest from > userspace is a huge benefit in terms of migration. > > Now, this is only half of the problem (and we're back to the CPU > model): most of these CPUs have various degrees of brokenness. Most of > the workarounds have to be implemented by the guest, and are keyed on > the MIDR values. So somehow, you need to be able to expose *all* the > possible MIDR values that a guest can observe in its lifetime. > > I have a vague prototype for that that I'd need to dust off and > finish, because that's also needed for this very silly construct > called big-little... And the third half of the problem is all of the other IP bits that get strung together into an SOC :) Errata that live beyond the CPU can become guest-visible (interconnect for example) and that becomes a bit difficult to express to the guest OS. So, beyond something like a big-little VM where the rest of the IP should be shared, I'm a bit fearful of migrating a VM cross-system. But hey, userspace is in the drivers seat and it can do as it pleases. Hopefully we wouldn't need a KVM-specific PV interface for MIDR enumeration. Perhaps the errata management spec could be expanded to describe a set of CPU implementations and associated errata... -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel