From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28237C7EE2A for ; Mon, 5 Jun 2023 09:55:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+VP0hWYptiRDhuzRDAigbMGkoAJqtvKj5glou73FPy0=; b=Yz7LkBP+Gk7P3v a4oUYcjKQ/Bm9YgPvjSs6439fe59eTMWXWJ701DPNhC9x0mkX3njMVMShClPojgx0I3vsHxPQdLSx Dq2X086exqEgHneUt11wxf/EzKspKJ5NQcrnWBx5Vq7iR7KzIfHgt3SrDdeoPs0sOnzNuLQ2XmPzh 9JAgY+IHTwPcRILQb/Ck+Rk8irBWcnqRNNO02knuaycO8SY41oSN6RGyqghhC6KEIGxpPxcI8pXDU 7aSkf8TbKkIkWtBDwq1Ij6Q5HIiW2vUgJi1REtpd5wcRA1b/hBcEc4se4wHmS04BOAkapJK7Ut4U8 3qIFoq4J0IZwZxtIiheQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q66vC-00EvQJ-09; Mon, 05 Jun 2023 09:54:42 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q66v8-00EvOi-1R for linux-arm-kernel@lists.infradead.org; Mon, 05 Jun 2023 09:54:40 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22949D75; Mon, 5 Jun 2023 02:55:19 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.24.244]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A0CD03F793; Mon, 5 Jun 2023 02:54:31 -0700 (PDT) Date: Mon, 5 Jun 2023 10:54:26 +0100 From: Mark Rutland To: Ravi Bangoria Cc: Krzysztof Kozlowski , "Peter Zijlstra (Intel)" , jolsa@kernel.org, irogers@google.com, bp@alien8.de, adrian.hunter@intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, "linux-samsung-soc@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "regressions@lists.linux.dev" Subject: Re: [REGRESSION][BISECT] perf/core: Remove pmu linear searching code Message-ID: References: <3abd3693-ad87-9abf-a762-337076638fcc@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230605_025438_530284_3F9BF20E X-CRM114-Status: GOOD ( 20.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 05, 2023 at 03:04:45PM +0530, Ravi Bangoria wrote: > On 05-Jun-23 12:40 PM, Mark Rutland wrote: > > On Sun, Jun 04, 2023 at 01:38:10PM +0200, Krzysztof Kozlowski wrote: > >> Hi, > >> > >> #regzbot introduced: 9551fbb64d09 > >> > >> Bisect pointed to commit 9551fbb64d09 ("perf/core: Remove pmu linear > >> searching code") as first one where all hardware events are gone from > >> perf for ARMv7 Exynos5422 board. > > > > I think that commit 9551fbb64d09 is just wrong. > > > > The commit message asserts: > > > > Searching for the right pmu by iterating over all pmus is no longer > > required since all pmus now *must* be present in the 'pmu_idr' list. > > So, remove linear searching code. > > > > ... and while each PMU has *some* entry in the pmu_idr list, for its dynamic > > type, that means that events with other types (e.g. PERF_TYPE_HARDWARE or > > PERF_TYPE_RAW) will fail to find a PMU in the IDR whereas they'd previously > > have been accepted by a PMU during the subsequent iteration over all PMUs. > > Not sure I follow. > > PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE are aliased to PERF_TYPE_RAW in > perf_init_event(). And PERF_TYPE_RAW should be present in pmu_idr if it > was registered using: > > perf_pmu_register(pmu, "name", PERF_TYPE_RAW); As I said, the PMUs get registered with a dynamic type, and there's no registration with PERF_TYPE_RAW. On arm/arm64 systems, *every* CPU PMU gets registered with: perf_pmu_register(pmu, name, -1); ... and *none* are registered with: perf_pmu_register(pmu, name, PERF_TYPE_RAW) ... so those all get a dynamic IDR type, and nothing gets placed into the IDR for PERF_TYPE_RAW, etc. We rely on the linear search to find a PMU that can handle PERF_TYPE_RAW, etc. I appreciate that's not ideal, but it's how it has worked for almost a decade now, so we can't change the userspace-visible behaviour. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel