From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A962C77B73 for ; Tue, 30 May 2023 13:39:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WKboJr+GBgouraPhov/cvc7Addf3cw5UYc45xRqyBlY=; b=olD3UFjZ0UCIkE FbIgYC71NLTfa85AlW5FspY4NjRi9w9uTBtCK6w72hXvICIASGKWafQfw6Po4GFhHqQRqEYFNn8Xd XTqNcHJWy3OGHyJ0D4DhcV/MHBxP2rPXh7xl6FdB48d4RQkH0Mn+D1i8whOw9Q9M0fCOxUsPCwl6a aSkj2KdZtW5NfCz+L+duhkMugdZKDFftLL9lVhAAXhURedkdgw4aRQjeVEoHY3bfRLLjIBSQNDubd srns0P75jrT9t4g8VAD3NtMgwO18Krn4hZ8Sm3uM2+EpWegzWpZNU/l/TJTbUfUAw2B5uxgisNRuf IjFA3+CdlJZX2aFF4nvw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q3zZD-00E4VB-1J; Tue, 30 May 2023 13:39:15 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q3zZ2-00E4Pg-0t for linux-arm-kernel@lists.infradead.org; Tue, 30 May 2023 13:39:05 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CC1D963045; Tue, 30 May 2023 13:39:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AFFF6C433EF; Tue, 30 May 2023 13:38:58 +0000 (UTC) Date: Tue, 30 May 2023 14:38:55 +0100 From: Catalin Marinas To: Jonathan Cameron Cc: Linus Torvalds , Christoph Hellwig , Robin Murphy , Arnd Bergmann , Greg Kroah-Hartman , Will Deacon , Marc Zyngier , Andrew Morton , Herbert Xu , Ard Biesheuvel , Isaac Manjarres , Saravana Kannan , Alasdair Kergon , Daniel Vetter , Joerg Roedel , Mark Brown , Mike Snitzer , "Rafael J. Wysocki" , linux-mm@kvack.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 00/15] mm, dma, arm64: Reduce ARCH_KMALLOC_MINALIGN to 8 Message-ID: References: <20230524171904.3967031-1-catalin.marinas@arm.com> <20230525133138.000014b4@Huawei.com> <20230526170740.000000df@Huawei.com> <20230526172930.000015f8@Huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230526172930.000015f8@Huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230530_063904_407597_BF078542 X-CRM114-Status: GOOD ( 36.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 26, 2023 at 05:29:30PM +0100, Jonathan Cameron wrote: > On Fri, 26 May 2023 17:07:40 +0100 > Jonathan Cameron wrote: > > On Thu, 25 May 2023 15:31:34 +0100 > > Catalin Marinas wrote: > > > On Thu, May 25, 2023 at 01:31:38PM +0100, Jonathan Cameron wrote: > > > > On Wed, 24 May 2023 18:18:49 +0100 > > > > Catalin Marinas wrote: > > > > > Another version of the series reducing the kmalloc() minimum alignment > > > > > on arm64 to 8 (from 128). Other architectures can easily opt in by > > > > > defining ARCH_KMALLOC_MINALIGN as 8 and selecting > > > > > DMA_BOUNCE_UNALIGNED_KMALLOC. > > > > > > > > > > The first 10 patches decouple ARCH_KMALLOC_MINALIGN from > > > > > ARCH_DMA_MINALIGN and, for arm64, limit the kmalloc() caches to those > > > > > aligned to the run-time probed cache_line_size(). On arm64 we gain the > > > > > kmalloc-{64,192} caches. > > > > > > > > > > The subsequent patches (11 to 15) further reduce the kmalloc() caches to > > > > > kmalloc-{8,16,32,96} if the default swiotlb is present by bouncing small > > > > > buffers in the DMA API. > > > > > > > > I think IIO_DMA_MINALIGN needs to switch to ARCH_DMA_MINALIGN as well. > > > > > > > > It's used to force static alignement of buffers with larger structures, > > > > to make them suitable for non coherent DMA, similar to your other cases. > > > > > > Ah, I forgot that you introduced that macro. However, at a quick grep, I > > > don't think this forced alignment always works as intended (irrespective > > > of this series). Let's take an example: > > > > > > struct ltc2496_driverdata { > > > /* this must be the first member */ > > > struct ltc2497core_driverdata common_ddata; > > > struct spi_device *spi; > > > > > > /* > > > * DMA (thus cache coherency maintenance) may require the > > > * transfer buffers to live in their own cache lines. > > > */ > > > unsigned char rxbuf[3] __aligned(IIO_DMA_MINALIGN); > > > unsigned char txbuf[3]; > > > }; > > > > > > The rxbuf is aligned to IIO_DMA_MINALIGN, the structure and its size as > > > well but txbuf is at an offset of 3 bytes from the aligned > > > IIO_DMA_MINALIGN. So basically any cache maintenance on rxbuf would > > > corrupt txbuf. > > > > That was intentional (though possibly wrong if I've misunderstood > > the underlying issue). > > > > For SPI controllers at least my understanding was that it is safe to > > assume that they won't trample on themselves. The driver doesn't > > touch the buffers when DMA is in flight - to do so would indeed result > > in corruption. > > > > So whilst we could end up with the SPI master writing stale data back > > to txbuf after the transfer it will never matter (as the value is unchanged). > > Any flushes in the other direction will end up flushing both rxbuf and > > txbuf anyway which is also harmless. > > Adding missing detail. As the driver never writes txbuf whilst any DMA > is going on, the second cache evict (to flush out any lines that have > crept back into cache after the flush - and write backs - pre DMA) will > find a clean line and will drop it without writing back - thus no corruption. Thanks for the clarification. One more thing, can the txbuf be written prior to the DMA_FROM_DEVICE transfer into rxbuf? Or the txbuf writing is always followed by a DMA_TO_DEVICE mapping (which would flush the cache line). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel