Re: [PATCH v3 11/20] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS

Re: [PATCH v3 11/20] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS

[Catalin Marinas]

On Thu, May 11, 2023 at 12:03:28PM +0100, Joey Gouly wrote:
> With PIE enabled, the swapper PTEs would have a Permission Indirection Index
> (PIIndex) of 0. A PIIndex of 0 is not currently used by any other PTEs.
> 
> To avoid using index 0 specifically for the swapper PTEs, mark them as
> PTE_UXN and PTE_WRITE, so that they map to a PAGE_KERNEL_EXEC equivalent.
> 
> This also adds PTE_WRITE to KPTI_NG_PTE_FLAGS, which was tested by booting
> with kpti=on.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>

It looks fine now.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v3 00/20] Permission Indirection Extension

[Mark Brown]

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On Thu, May 11, 2023 at 12:03:17PM +0100, Joey Gouly wrote:
> Hi all,
> 
> This series implements the Permission Indirection Extension introduced in 2022
> VMSA enhancements [1].

I've been using this in my general development and in particular with my
GCS work and everything seems to be working so:

Tested-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v3 08/20] KVM: arm64: Save/restore TCR2_EL1

[Catalin Marinas]

On Thu, May 11, 2023 at 12:03:25PM +0100, Joey Gouly wrote:
> Define the new system register TCR2_EL1 and context switch it.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Zenghui Yu <yuzenghui@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

Marc, I think the comments you had previously on this patch have been
addressed (using reset_val now instead of reset_unknown).

When you get around, please ack so that I can queue it through the arm64
tree.

Thanks.

-- 
Catalin

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Re: [PATCH v3 09/20] KVM: arm64: Save/restore PIE registers

[Catalin Marinas]

On Thu, May 11, 2023 at 12:03:26PM +0100, Joey Gouly wrote:
> Define the new system registers that PIE introduces and context switch them.
> The PIE feature is still hidden from the ID register, and not exposed to a VM.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Zenghui Yu <yuzenghui@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
> ---
>  arch/arm64/include/asm/kvm_host.h          | 4 ++++
>  arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 8 ++++++++
>  arch/arm64/kvm/sys_regs.c                  | 2 ++
>  3 files changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> index f2cfb9ef1eeb..d9f079fbdaf4 100644
> --- a/arch/arm64/include/asm/kvm_host.h
> +++ b/arch/arm64/include/asm/kvm_host.h
> @@ -340,6 +340,10 @@ enum vcpu_sysreg {
>  	TFSR_EL1,	/* Tag Fault Status Register (EL1) */
>  	TFSRE0_EL1,	/* Tag Fault Status Register (EL0) */
>  
> +	/* Permission Indirection Extension registers */
> +	PIR_EL1,       /* Permission Indirection Register 1 (EL1) */
> +	PIRE0_EL1,     /*  Permission Indirection Register 0 (EL1) */

These have been moved outside of the *_EL2 range as Marc asked. It looks
fine to me, waiting for an Ack from Marc/Oliver.

-- 
Catalin

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Re: [PATCH v3 08/20] KVM: arm64: Save/restore TCR2_EL1

[Marc Zyngier]

On Thu, 11 May 2023 12:03:25 +0100,
Joey Gouly <joey.gouly@arm.com> wrote:
> 
> Define the new system register TCR2_EL1 and context switch it.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Zenghui Yu <yuzenghui@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

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Re: [PATCH v3 09/20] KVM: arm64: Save/restore PIE registers

[Marc Zyngier]

On Thu, 11 May 2023 12:03:26 +0100,
Joey Gouly <joey.gouly@arm.com> wrote:
> 
> Define the new system registers that PIE introduces and context switch them.
> The PIE feature is still hidden from the ID register, and not exposed to a VM.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Zenghui Yu <yuzenghui@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

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Re: [PATCH v3 10/20] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Marc Zyngier]

On Thu, 11 May 2023 12:03:27 +0100,
Joey Gouly <joey.gouly@arm.com> wrote:
> 
> Now that KVM context switches the appropriate registers, expose ID_AA64MMFR3_EL1
> to guests to allow them to use the new features.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Zenghui Yu <yuzenghui@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>

Reviewed-by: Marc Zyngier <maz@kernel.org>

	M.

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Re: [PATCH v3 00/20] Permission Indirection Extension

[Catalin Marinas]

On Thu, May 11, 2023 at 12:03:17PM +0100, Joey Gouly wrote:
> Joey Gouly (20):
>   arm64/sysreg: Add ID register ID_AA64MMFR3
>   arm64/sysreg: add system registers TCR2_ELx
>   arm64/sysreg: update HCRX_EL2 register
>   arm64/sysreg: add PIR*_ELx registers
>   arm64: cpufeature: add system register ID_AA64MMFR3
>   arm64: cpufeature: add TCR2 cpucap
>   arm64: cpufeature: add Permission Indirection Extension cpucap
>   KVM: arm64: Save/restore TCR2_EL1
>   KVM: arm64: Save/restore PIE registers
>   KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
>   arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
>   arm64: add PTE_WRITE to PROT_SECT_NORMAL
>   arm64: reorganise PAGE_/PROT_ macros
>   arm64: disable EL2 traps for PIE
>   arm64: add encodings of PIRx_ELx registers
>   arm64: enable Permission Indirection Extension (PIE)
>   arm64: transfer permission indirection settings to EL2
>   arm64: Document boot requirements for PIE
>   KVM: selftests: get-reg-list: support ID register features
>   KVM: selftests: get-reg-list: add Permission Indirection registers

For some reason lore.kernel.org doesn't have this series, though it made
it to infradead (and this archive:
http://lists.openwrt.org/pipermail/linux-arm-kernel/2023-May/833014.html).

I applied it manually to the arm64 for-next/feat_s1pie (I don't have a
b4 automated reply for it).

Patch 14 conflicts with Kristina's series (for-next/feat_mops) and I
solved it in the merge resolution in for-next/core but this would get
lost when I redo the topic branch merges.

You might as well rebase this series on top of the arm64
for-next/feat_mops and repost so that we have the Link: tag as well.

Thanks.

-- 
Catalin

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