From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 518EBC7EE29 for ; Thu, 8 Jun 2023 14:16:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kn2fkThiOXfh3jSZdZE4Ky73HGY9NR6oaX0qR2zq8n0=; b=C9F+VepJyKeAAg esxoAx/il428J4wpzTPGtajDSeucA0U3IpVQtAs82TlC9mtMzNAKxzBXBjjvCyRZz9fXOqSeQ2lh9 Wnb8qRpB6GzxJquGgiL7e55fOZW5juONC+494oRlY5O104q3gHLlYL8CeeHHaEfFyOC/Q7dogrJMX IfK///fmxsxvXQbLFFLBrJXVzuujdw8Dnh8fhz9Ur/7RZhDbT8KEMuCG84hRud4zzRMbK9Ssn0lvn ZM1ha5TKV9sLsB/tsBrK/03BjSnrAN18dmfbDUjmjnlicPOh8OdRJsHD6DtD7yUpEe9C56vtYQloF hSXcZ9mP6KBDGk9KTfMg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q7GRB-009b6o-1l; Thu, 08 Jun 2023 14:16:29 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q7GR8-009b5x-0M for linux-arm-kernel@lists.infradead.org; Thu, 08 Jun 2023 14:16:27 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 55456AB6; Thu, 8 Jun 2023 07:17:06 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.24.103]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 258363F6C4; Thu, 8 Jun 2023 07:16:19 -0700 (PDT) Date: Thu, 8 Jun 2023 15:16:16 +0100 From: Mark Rutland To: "Ivan T. Ivanov" Cc: Will Deacon , Catalin Marinas , Mark Brown , Shawn Guo , Dong Aisheng , Frank Li , Jason Liu , linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com Subject: Re: [PATCH v2] arm64: errata: Add NXP iMX8QM workaround for A53 Cache coherency issue Message-ID: References: <20230420112952.28340-1-iivanov@suse.de> <20230602103436.GA16785@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230608_071626_199594_057E5225 X-CRM114-Status: GOOD ( 23.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jun 08, 2023 at 04:39:29PM +0300, Ivan T. Ivanov wrote: > On 06-02 11:34, Will Deacon wrote: > > On Thu, Apr 20, 2023 at 02:29:52PM +0300, Ivan T. Ivanov wrote: > > > According to NXP errata document[1] i.MX8QuadMax SoC suffers from > > > serious cache coherence issue. It was also mentioned in initial > > > support[2] for imx8qm mek machine. > > > > > > I chose to use an ALTERNATIVE() framework, instead downstream solution[3], > > > for this issue with the hope to reduce effect of this fix on unaffected > > > platforms. > > > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > > > index 4a79ba100799..265b6334291b 100644 > > > --- a/arch/arm64/kernel/traps.c > > > +++ b/arch/arm64/kernel/traps.c > > > @@ -556,6 +556,11 @@ static void user_cache_maint_handler(unsigned long esr, struct pt_regs *regs) > > > __user_cache_maint("dc civac", address, ret); > > > break; > > > case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ > > > + if (cpus_have_final_cap(ARM64_WORKAROUND_NXP_ERR050104)) { > > > + asm volatile("ic ialluis"); > > > > Hmm, one oddity here is that you can pass a faulting address and not see > > the fault. It looks like that's already IMP DEF, so it's probably ok, but > > might be worth a comment. > > I am not sure what should be expected behavior, but I could > add comment, sure. Another option is to make this: case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ __user_cache_maint("ic ivau", address, ret) if (cpus_have_final_cap(ARM64_WORKAROUND_NXP_ERR050104) && !ret) asm volatile("ic ialluis"); break; Which'll ensure that if the regular IC IVAU faults we'll handle that, and if not we'll do the IC IALLUIS. I think that looks a bit cleaner, too. > > Finally, how come you don't need to upgrade I-cache invalidation by-VA > > in the kernel? It looks like you're only handling operations trapped > > from EL0. > > Hm, I was thinking that __tlbi() is taking care for this or you mean > something else, like locations in assembler.h? The __tlbi macro handles only TLBI instructions. The trap handler above *only* handles IC instructions trapped from userspace; we have IC IVAU instructions elsewhere in the kernel (e.g. arch/arm64/mm/cache.S). Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel