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From: Oliver Upton To: Reiji Watanabe Cc: Marc Zyngier , kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH 1/1] KVM: arm64: PMU: Avoid inappropriate use of host's PMUVer Message-ID: References: <20230610194510.4146549-1-reijiw@google.com> <20230611045430.evkcp4py4yuw5qgr@google.com> <20230611160105.orvjohigsaevkcrf@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230611160105.orvjohigsaevkcrf@google.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230612_123645_373721_9875A6DE X-CRM114-Status: GOOD ( 20.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Jun 11, 2023 at 09:01:05AM -0700, Reiji Watanabe wrote: [...] > > Suppose KVM is running on a v3p5+ implementation, but userspace has set > > ID_AA64DFR0_EL1.PMUVer to v3p0. In this case the read of PMCEID1_EL0 on > > the preceding line would advertise the STALL_SLOT event, and KVM fails > > to mask it due to the ID register value. The fact we do not support the > > event is an invariant, in the worst case we wind up clearing a bit > > that's already 0. > > As far as I checked ArmARM, the STALL_SLOT event can be supported on > any PMUv3 version (including on v3p0). Assuming that is true, I don't > see any reason to not expose the event to the guest in this particular > example. Or can the STALL_SLOT event only be implemented from certain > versions of PMUv3 ? Well, users of the event don't get the full picture w/o PMMIR_EL1.SLOTS, which is only available on v3p4+. We probably should start exposing the register + event (separate from this change). > > This is why I'd suggested just unconditionally clearing the bit. While > > When the hardware supports the STALL_SLOT event (again, I assume any > PMUv3 version hardware can support the event), and the guest's PMUVer > is older than v3p4, what is the reason why we want to clear the bit ? What's the value of the event w/o PMMIR_EL1? I agree there's no fundamental issue with letting it past, but I'd rather we start exposing the feature when we provide all the necessary detail. -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel