From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97494EB64D9 for ; Wed, 14 Jun 2023 10:27:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dCSBfHg2+xuPa7CMlgVfs8IFdx4hNlAuISKzef6oqoI=; b=F0m6+ztK3XpRQ7 e/YhIzzqeXN+HuDpFVskWgU1ieVX/tIgUN2NXVO4v3uH0NJ0fWFq9VU6Z4h3sR/n3YyZCWOjj7jGv E4VUGIcahpJiv3wgIhdHeZJJIK6GR4ZCMKjZQ55capI5NEgs7vPX1I4mhrivkBhSG6O2+17ShTCV1 CgtZiw1uKUuHzXYlMjTCb98AgCASKwPx22E0XRNFZhrhzhLRY0lreQjPsva0U0nVIEAdUzSZyhvcQ kkhWna+G6KsucxEIatsl5liiBBIIGYDqkh2FHpDahxy6hWORo/bv2TI2Rrzah1Puw3TsKALx0ppBf pZZyTp0IZU+J3spoj4Sg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q9Nic-00BDQA-08; Wed, 14 Jun 2023 10:27:14 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q9NiZ-00BDPM-2s for linux-arm-kernel@lists.infradead.org; Wed, 14 Jun 2023 10:27:13 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 63A18616A3; Wed, 14 Jun 2023 10:27:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C59E7C433C9; Wed, 14 Jun 2023 10:27:09 +0000 (UTC) Date: Wed, 14 Jun 2023 11:27:07 +0100 From: Catalin Marinas To: Jamie Iles Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, Will Deacon , Mark Rutland Subject: Re: [PATCH] arm64/mm: remove now-superfluous ISBs from TTBR writes Message-ID: References: <20230613141959.92697-1-quic_jiles@quicinc.com> <7f28549a-fbae-11ec-555a-c0b798c54c03@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230614_032711_975609_93A36C4B X-CRM114-Status: GOOD ( 18.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 14, 2023 at 11:09:38AM +0100, Jamie Iles wrote: > On Wed, Jun 14, 2023 at 03:35:03PM +0530, Anshuman Khandual wrote: > > On 6/13/23 19:49, Jamie Iles wrote: > > > At the time of authoring 7655abb95386 ("arm64: mm: Move ASID from TTBR0 > > > to TTBR1"), the Arm ARM did not specify any ordering guarantees for > > > direct writes to TTBR0_ELx and TTBR1_ELx and so an ISB was required > > > after each write to ensure TLBs would only be populated from the > > > expected (or reserved tables). > > > > > > In a recent update to the Arm ARM, the requirements have been relaxed to > > > reflect the implementation of current CPUs and required implementation > > > of future CPUs to read (RDYDPX in D8.2.3 Translation table base address > > > register): > > > > But what about the existing CPUs that might still require an ISB after > > each individual write into TTBR0/1_EL1 ? Would they be impacted if the > > ISB get dropped ? > > For this retrospective change Arm verify that this is the current > behaviour of existing CPUs both by Arm Ltd and licensees. There should > be no current CPUs that require these ISBs. Indeed. If we do come across one, we may have to bring some of these back as errata workaround. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel