From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C623C001B0 for ; Thu, 13 Jul 2023 19:09:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ryLuGxxJT64L6LPwWo3u//FV9H7xu83ziOSG/9RS4QY=; b=ws2eMqsjkCCVuw C7YVNSmbPsXKJrXqWioTd1tmNWLMT4fodYHFJ8qFy+yEJy5QxYASNtTBcXUaYHhkbDjXkmSxvTMJO 6gttjrpp2yvmZjgsMWZhd6dMcnM8BL72HDA/Q8MOcEiCNKl64Gp33i1MFWhWn/DMl1pNwN6lskR2Y hPlPWQ9UMdEE2urOoTZwsJm6LqWquytURjnWIfe35X4I5s97RcCUK0mdB13kKHkfrpxOYTXy7PziR L/xkqS7E5zF7jp1wdJYqk5Qz8A9bXu5QK7/dniaYvfBErhRuJE5sGMmQp9yvDiW72Z4++ED5QE353 fVzZUgQZJUs5zb5aA/JA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qK1gU-004CyN-2M; Thu, 13 Jul 2023 19:09:02 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qK1gP-004CxC-1H for linux-arm-kernel@lists.infradead.org; Thu, 13 Jul 2023 19:09:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 716E61570; Thu, 13 Jul 2023 12:09:35 -0700 (PDT) Received: from FVFF77S0Q05N.cambridge.arm.com (unknown [10.37.36.116]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1495E3F67D; Thu, 13 Jul 2023 12:08:50 -0700 (PDT) Date: Thu, 13 Jul 2023 20:08:48 +0100 From: Mark Rutland To: "Aiqun(Maria) Yu" Cc: Will Deacon , corbet@lwn.net, catalin.marinas@arm.com, maz@kernel.org, quic_pkondeti@quicinc.com, quic_kaushalk@quicinc.com, quic_satyap@quicinc.com, quic_shashim@quicinc.com, quic_songxue@quicinc.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: Add the arm64.nolse_atomics command line option Message-ID: References: <20230710093751.GC32673@willie-the-truck> <5cf15f85-0397-96f7-4110-13494551b53b@quicinc.com> <20230711082226.GA1554@willie-the-truck> <84f0994a-26de-c20a-a32f-ec8fe41df3a3@quicinc.com> <20230711102510.GA1809@willie-the-truck> <67c2621f-4cad-2495-9785-7737246d3e90@quicinc.com> <604ac52d-4336-744f-2ab8-44d1c93fbaa8@quicinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230713_120857_502510_CE5AF6B0 X-CRM114-Status: GOOD ( 14.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 13, 2023 at 10:08:34PM +0800, Aiqun(Maria) Yu wrote: > On 7/13/2023 7:20 PM, Mark Rutland wrote: > > Are you saying that LSE atomics to *cacheable* mappings do not work on your > > system? > > > > Specifically, when using a Normal Inner-Shareable Inner-Writeback > > Outer-Writeback mapping, do the LSE atomics work or not work? > *cacheable* mapping have the LSE atomic is not working if far atomic is > performed. Thanks for confirming; the fact that this doesn't work on *cacheable* memory is definitely a major issue. I think everyone is confused here because of the earlier mention of non-cachable accesses (which don't matter). I know that some CPU implementations have EL3 control bits to force LSE atomics to be performed near (e.g. in Cortex-A55, the CPUECTLR.ATOM control bits), which would avoid the issue while still allowing the LSE atomics to be used. If those can be configured in EL3 firmware, that would be a preferable workaround. Can you say which CPUs are integrated in this system? and/or can you check if such control bits exist? Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel