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Tue, 18 Jul 2023 11:29:28 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1qLpRu-002ayW-Jq; Tue, 18 Jul 2023 15:29:26 -0300 Date: Tue, 18 Jul 2023 15:29:26 -0300 From: Jason Gunthorpe To: Andrew Morton Cc: Alistair Popple , ajd@linux.ibm.com, catalin.marinas@arm.com, fbarrat@linux.ibm.com, iommu@lists.linux.dev, jhubbard@nvidia.com, kevin.tian@intel.com, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, nicolinc@nvidia.com, npiggin@gmail.com, robin.murphy@arm.com, seanjc@google.com, will@kernel.org, x86@kernel.org, zhi.wang.linux@gmail.com Subject: Re: [PATCH 3/4] mmu_notifiers: Call arch_invalidate_secondary_tlbs() when invalidating TLBs Message-ID: References: <791a6c1c4a79de6f99bffc594b53a39a6234e87f.1689666760.git-series.apopple@nvidia.com> <20230718111759.5642b4c4ffd72ddd9c8aa29f@linux-foundation.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230718111759.5642b4c4ffd72ddd9c8aa29f@linux-foundation.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230718_193032_427869_CA4149B1 X-CRM114-Status: GOOD ( 21.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 18, 2023 at 11:17:59AM -0700, Andrew Morton wrote: > On Tue, 18 Jul 2023 17:56:17 +1000 Alistair Popple wrote: > > > The arch_invalidate_secondary_tlbs() is an architecture specific mmu > > notifier used to keep the TLB of secondary MMUs such as an IOMMU in > > sync with the CPU page tables. Currently it is called from separate > > code paths to the main CPU TLB invalidations. This can lead to a > > secondary TLB not getting invalidated when required and makes it hard > > to reason about when exactly the secondary TLB is invalidated. > > > > To fix this move the notifier call to the architecture specific TLB > > maintenance functions for architectures that have secondary MMUs > > requiring explicit software invalidations. > > > > This fixes a SMMU bug on ARM64. On ARM64 PTE permission upgrades > > require a TLB invalidation. This invalidation is done by the > > architecutre specific ptep_set_access_flags() which calls > > flush_tlb_page() if required. However this doesn't call the notifier > > resulting in infinite faults being generated by devices using the SMMU > > if it has previously cached a read-only PTE in it's TLB. > > This sounds like a pretty serious bug. Can it happen in current > released kernels? If so, is a -stable backport needed? There are currently no in-kernel drivers using the IOMMU SVA API, so the impact for -stable is sort of muted. But it is serious if you are unlucky to hit it. Jason _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel