[PATCH v2 1/3] perf/imx_ddr: speed up overflow frequency of cycle counter

[PATCH v2 1/3] perf/imx_ddr: speed up overflow frequency of cycle counter

[Xu Yang]

For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least
4 times as often as other events. Due to byte counters will count for any
event configured, it will overflow more often. And if byte counters
overflow that related counters would stop since they share the COUNTER_CNTL
We can speed up cycle counter overflow frequency by setting counter
parameter (CP) field of cycle counter. In this way, we can avoid stop
counting byte counters when interrupt didn't come and the byte counters
can be fetched or updated from each cycle counter overflow interrupt.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes in v2:
 - improve if condition
---
 drivers/perf/fsl_imx8_ddr_perf.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index 5222ba1e79d0..039069756bbc 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -28,6 +28,8 @@
 #define CNTL_CLEAR_MASK		0xFFFFFFFD
 #define CNTL_OVER_MASK		0xFFFFFFFE
 
+#define CNTL_CP_SHIFT		16
+#define CNTL_CP_MASK		(0xFF << CNTL_CP_SHIFT)
 #define CNTL_CSV_SHIFT		24
 #define CNTL_CSV_MASK		(0xFFU << CNTL_CSV_SHIFT)
 
@@ -427,6 +429,19 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
 		writel(0, pmu->base + reg);
 		val = CNTL_EN | CNTL_CLEAR;
 		val |= FIELD_PREP(CNTL_CSV_MASK, config);
+
+		/*
+		 * Workaround for i.MX8MP:
+		 * Common counters and byte counters share the same COUNTER_CNTL,
+		 * and byte counters could overflow before cycle counter. Need set
+		 * counter parameter(CP) of cycle counter to give it initial value
+		 * which can speed up cycle counter overflow frequency.
+		 */
+		if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
+			if (counter == EVENT_CYCLES_COUNTER)
+				val |= FIELD_PREP(CNTL_CP_MASK, 0xf0);
+		}
+
 		writel(val, pmu->base + reg);
 	} else {
 		/* Disable counter */
-- 
2.34.1


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[PATCH v2 2/3] perf/imx_ddr: adjust counter result after read cycle counter

[Xu Yang]

Because we initialize CP filed to shorten counter0 overflow time, the cycle
counter will start couting from a fixed/base value each time. We need to
remove the base from the result too. Therefore, we could get precise result
from cycle counter.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes in v2:
 - improve if condition
---
 drivers/perf/fsl_imx8_ddr_perf.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index 039069756bbc..d65200d4e96e 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -481,6 +481,12 @@ static void ddr_perf_event_update(struct perf_event *event)
 	int ret;
 
 	new_raw_count = ddr_perf_read_counter(pmu, counter);
+	/* Workaround for i.MX8MP */
+	if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
+		if (counter == EVENT_CYCLES_COUNTER)
+			new_raw_count -= 0xF0000000;
+	}
+
 	local64_add(new_raw_count, &event->count);
 
 	/*
-- 
2.34.1


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[PATCH v2 3/3] perf/imx_ddr: don't enable counter0 if none of 4 counters are used

[Xu Yang]

In current driver, counter0 will be enabled after ddr_perf_pmu_enable()
is called even though none of the 4 counters are used. This will cause
counter0 continue to count until ddr_perf_pmu_disabled() is called. If
pmu is not disabled all the time, the pmu interrupt will be asserted
from time to time due to counter0 will overflow and irq handler will
clear it. It's not an expected behavior. This patch will not enable
counter0 if none of 4 counters are used.

Fixes: 9a66d36cc7ac ("drivers/perf: imx_ddr: Add DDR performance counter support to perf")
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes in v2:
 - add active events count as suggested from Frank
---
 drivers/perf/fsl_imx8_ddr_perf.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index d65200d4e96e..761e45f21092 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -103,6 +103,7 @@ struct ddr_pmu {
 	const struct fsl_ddr_devtype_data *devtype_data;
 	int irq;
 	int id;
+	int active_count;
 };
 
 static ssize_t ddr_perf_identifier_show(struct device *dev,
@@ -516,6 +517,9 @@ static void ddr_perf_event_start(struct perf_event *event, int flags)
 
 	ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
 
+	if (counter != EVENT_CYCLES_COUNTER)
+		pmu->active_count++;
+
 	hwc->state = 0;
 }
 
@@ -569,6 +573,9 @@ static void ddr_perf_event_stop(struct perf_event *event, int flags)
 	ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
 	ddr_perf_event_update(event);
 
+	if (counter != EVENT_CYCLES_COUNTER)
+		pmu->active_count--;
+
 	hwc->state |= PERF_HES_STOPPED;
 }
 
@@ -589,7 +596,8 @@ static void ddr_perf_pmu_enable(struct pmu *pmu)
 	struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
 
 	/* enable cycle counter if cycle is not active event list */
-	if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
+	if ((ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
+		&& ddr_pmu->active_count > 0)
 		ddr_perf_counter_enable(ddr_pmu,
 				      EVENT_CYCLES_ID,
 				      EVENT_CYCLES_COUNTER,
@@ -600,7 +608,8 @@ static void ddr_perf_pmu_disable(struct pmu *pmu)
 {
 	struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
 
-	if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
+	if ((ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
+		&& ddr_pmu->active_count > 0)
 		ddr_perf_counter_enable(ddr_pmu,
 				      EVENT_CYCLES_ID,
 				      EVENT_CYCLES_COUNTER,
-- 
2.34.1


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RE: [PATCH v2 2/3] perf/imx_ddr: adjust counter result after read cycle counter

[Frank Li]

> -----Original Message-----
> From: Xu Yang <xu.yang_2@nxp.com>
> Sent: Thursday, July 13, 2023 5:38 AM
> To: Frank Li <frank.li@nxp.com>
> Cc: will@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; dl-linux-imx <linux-
> imx@nxp.com>; linux-arm-kernel@lists.infradead.org
> Subject: [PATCH v2 2/3] perf/imx_ddr: adjust counter result after read cycle
> counter
> 
> Because we initialize CP filed to shorten counter0 overflow time, the cycle
> counter will start couting from a fixed/base value each time. We need to
> remove the base from the result too. Therefore, we could get precise result
> from cycle counter.
> 
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> 
> ---
> Changes in v2:
>  - improve if condition
> ---
>  drivers/perf/fsl_imx8_ddr_perf.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c
> b/drivers/perf/fsl_imx8_ddr_perf.c
> index 039069756bbc..d65200d4e96e 100644
> --- a/drivers/perf/fsl_imx8_ddr_perf.c
> +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> @@ -481,6 +481,12 @@ static void ddr_perf_event_update(struct
> perf_event *event)
>  	int ret;
> 
>  	new_raw_count = ddr_perf_read_counter(pmu, counter);
> +	/* Workaround for i.MX8MP */
> +	if (pmu->devtype_data->quirks &
> DDR_CAP_AXI_ID_FILTER_ENHANCED) {
> +		if (counter == EVENT_CYCLES_COUNTER)
> +			new_raw_count -= 0xF0000000;

[Frank Li] Do you means
	new_raw_count &= 0x0FFFFFFF? to mask bit 24..31?

> +	}
> +
>  	local64_add(new_raw_count, &event->count);
> 
>  	/*
> --
> 2.34.1


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RE: [PATCH v2 2/3] perf/imx_ddr: adjust counter result after read cycle counter

[Xu Yang]

-----Original Message-----
> 
> Because we initialize CP filed to shorten counter0 overflow time, the cycle
> counter will start couting from a fixed/base value each time. We need to
> remove the base from the result too. Therefore, we could get precise result
> from cycle counter.
> 
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> 
> ---
> Changes in v2:
>  - improve if condition
> ---
>  drivers/perf/fsl_imx8_ddr_perf.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c
> b/drivers/perf/fsl_imx8_ddr_perf.c
> index 039069756bbc..d65200d4e96e 100644
> --- a/drivers/perf/fsl_imx8_ddr_perf.c
> +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> @@ -481,6 +481,12 @@ static void ddr_perf_event_update(struct
> perf_event *event)
>  	int ret;
> 
>  	new_raw_count = ddr_perf_read_counter(pmu, counter);
> +	/* Workaround for i.MX8MP */
> +	if (pmu->devtype_data->quirks &
> DDR_CAP_AXI_ID_FILTER_ENHANCED) {
> +		if (counter == EVENT_CYCLES_COUNTER)
> +			new_raw_count -= 0xF0000000;

[Frank Li] Do you means
	new_raw_count &= 0x0FFFFFFF? to mask bit 24..31?

Yes, it can be this way too. Do I need change it in v3?

Thanks,
Xu Yang

> +	}
> +
>  	local64_add(new_raw_count, &event->count);
> 
>  	/*
> --
> 2.34.1


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Re: [PATCH v2 1/3] perf/imx_ddr: speed up overflow frequency of cycle counter

[Mark Rutland]

On Thu, Jul 13, 2023 at 06:37:56PM +0800, Xu Yang wrote:
> For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least
> 4 times as often as other events. Due to byte counters will count for any
> event configured, it will overflow more often. And if byte counters
> overflow that related counters would stop since they share the COUNTER_CNTL
> We can speed up cycle counter overflow frequency by setting counter
> parameter (CP) field of cycle counter. In this way, we can avoid stop
> counting byte counters when interrupt didn't come and the byte counters
> can be fetched or updated from each cycle counter overflow interrupt.
> 
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> 
> ---
> Changes in v2:
>  - improve if condition
> ---
>  drivers/perf/fsl_imx8_ddr_perf.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
> index 5222ba1e79d0..039069756bbc 100644
> --- a/drivers/perf/fsl_imx8_ddr_perf.c
> +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> @@ -28,6 +28,8 @@
>  #define CNTL_CLEAR_MASK		0xFFFFFFFD
>  #define CNTL_OVER_MASK		0xFFFFFFFE
>  
> +#define CNTL_CP_SHIFT		16
> +#define CNTL_CP_MASK		(0xFF << CNTL_CP_SHIFT)
>  #define CNTL_CSV_SHIFT		24
>  #define CNTL_CSV_MASK		(0xFFU << CNTL_CSV_SHIFT)
>  
> @@ -427,6 +429,19 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
>  		writel(0, pmu->base + reg);
>  		val = CNTL_EN | CNTL_CLEAR;
>  		val |= FIELD_PREP(CNTL_CSV_MASK, config);
> +
> +		/*
> +		 * Workaround for i.MX8MP:
> +		 * Common counters and byte counters share the same COUNTER_CNTL,
> +		 * and byte counters could overflow before cycle counter. Need set
> +		 * counter parameter(CP) of cycle counter to give it initial value
> +		 * which can speed up cycle counter overflow frequency.
> +		 */

From the comments on path 2, it sounds like this "counter parameter" sets bits
[31..28] of the counter value, is that correct?

Assuming so, could we please update this comment to say:

	/*
	 * On i.MX8MP we need to bias the cycle counter to overflow more often.
	 * We do this by initializing bits [31:28] of the counter value via the
	 * COUNTER_CTRL Counter Parameter (CP) field.
	 *
	 * See ddr_perf_counter_enable() for more details.
	 */

Thanks,
Mark.

> +		if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
> +			if (counter == EVENT_CYCLES_COUNTER)
> +				val |= FIELD_PREP(CNTL_CP_MASK, 0xf0);
> +		}
> +
>  		writel(val, pmu->base + reg);
>  	} else {
>  		/* Disable counter */
> -- 
> 2.34.1
> 

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Re: [PATCH v2 2/3] perf/imx_ddr: adjust counter result after read cycle counter

[Mark Rutland]

On Thu, Jul 13, 2023 at 06:37:57PM +0800, Xu Yang wrote:
> Because we initialize CP filed to shorten counter0 overflow time, the cycle
> counter will start couting from a fixed/base value each time. We need to
> remove the base from the result too. Therefore, we could get precise result
> from cycle counter.

This means that patch 1 is incomplete; please fold this into patch 1.

> 
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> 
> ---
> Changes in v2:
>  - improve if condition
> ---
>  drivers/perf/fsl_imx8_ddr_perf.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
> index 039069756bbc..d65200d4e96e 100644
> --- a/drivers/perf/fsl_imx8_ddr_perf.c
> +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> @@ -481,6 +481,12 @@ static void ddr_perf_event_update(struct perf_event *event)
>  	int ret;
>  
>  	new_raw_count = ddr_perf_read_counter(pmu, counter);
> +	/* Workaround for i.MX8MP */
> +	if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
> +		if (counter == EVENT_CYCLES_COUNTER)
> +			new_raw_count -= 0xF0000000;
> +	}

I think as Frank suggested, it would be clearer to have a mask, and I think
this should have a comment:

	/*
	 * Remove the bias applied in ddr_perf_counter_enable().
	 */
	if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
		if (counter == EVENT_CYCLES_COUNTER)
			new_raw_count &= 0x0fffffff;
	}

Thanks,
Mark.

> +
>  	local64_add(new_raw_count, &event->count);
>  
>  	/*
> -- 
> 2.34.1
> 

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Re: [PATCH v2 3/3] perf/imx_ddr: don't enable counter0 if none of 4 counters are used

[Mark Rutland]

On Thu, Jul 13, 2023 at 06:37:58PM +0800, Xu Yang wrote:
> In current driver, counter0 will be enabled after ddr_perf_pmu_enable()
> is called even though none of the 4 counters are used. This will cause
> counter0 continue to count until ddr_perf_pmu_disabled() is called. If
> pmu is not disabled all the time, the pmu interrupt will be asserted
> from time to time due to counter0 will overflow and irq handler will
> clear it. It's not an expected behavior. This patch will not enable
> counter0 if none of 4 counters are used.
> 
> Fixes: 9a66d36cc7ac ("drivers/perf: imx_ddr: Add DDR performance counter support to perf")
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

Acked-by: Mark Rutland <mark.rutland@arm.com>

I assume that you'll send this as part of a v3 given the comments on patches 1
and 2.

Thanks,
Mark.

> 
> ---
> Changes in v2:
>  - add active events count as suggested from Frank
> ---
>  drivers/perf/fsl_imx8_ddr_perf.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
> index d65200d4e96e..761e45f21092 100644
> --- a/drivers/perf/fsl_imx8_ddr_perf.c
> +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> @@ -103,6 +103,7 @@ struct ddr_pmu {
>  	const struct fsl_ddr_devtype_data *devtype_data;
>  	int irq;
>  	int id;
> +	int active_count;
>  };
>  
>  static ssize_t ddr_perf_identifier_show(struct device *dev,
> @@ -516,6 +517,9 @@ static void ddr_perf_event_start(struct perf_event *event, int flags)
>  
>  	ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
>  
> +	if (counter != EVENT_CYCLES_COUNTER)
> +		pmu->active_count++;
> +
>  	hwc->state = 0;
>  }
>  
> @@ -569,6 +573,9 @@ static void ddr_perf_event_stop(struct perf_event *event, int flags)
>  	ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
>  	ddr_perf_event_update(event);
>  
> +	if (counter != EVENT_CYCLES_COUNTER)
> +		pmu->active_count--;
> +
>  	hwc->state |= PERF_HES_STOPPED;
>  }
>  
> @@ -589,7 +596,8 @@ static void ddr_perf_pmu_enable(struct pmu *pmu)
>  	struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
>  
>  	/* enable cycle counter if cycle is not active event list */
> -	if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
> +	if ((ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
> +		&& ddr_pmu->active_count > 0)
>  		ddr_perf_counter_enable(ddr_pmu,
>  				      EVENT_CYCLES_ID,
>  				      EVENT_CYCLES_COUNTER,
> @@ -600,7 +608,8 @@ static void ddr_perf_pmu_disable(struct pmu *pmu)
>  {
>  	struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
>  
> -	if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
> +	if ((ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
> +		&& ddr_pmu->active_count > 0)
>  		ddr_perf_counter_enable(ddr_pmu,
>  				      EVENT_CYCLES_ID,
>  				      EVENT_CYCLES_COUNTER,
> -- 
> 2.34.1
> 

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RE: [EXT] Re: [PATCH v2 1/3] perf/imx_ddr: speed up overflow frequency of cycle counter

[Xu Yang]

Hi Mark,

> On Thu, Jul 13, 2023 at 06:37:56PM +0800, Xu Yang wrote:
> > For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least
> > 4 times as often as other events. Due to byte counters will count for any
> > event configured, it will overflow more often. And if byte counters
> > overflow that related counters would stop since they share the COUNTER_CNTL
> > We can speed up cycle counter overflow frequency by setting counter
> > parameter (CP) field of cycle counter. In this way, we can avoid stop
> > counting byte counters when interrupt didn't come and the byte counters
> > can be fetched or updated from each cycle counter overflow interrupt.
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> >
> > ---
> > Changes in v2:
> >  - improve if condition
> > ---
> >  drivers/perf/fsl_imx8_ddr_perf.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
> > index 5222ba1e79d0..039069756bbc 100644
> > --- a/drivers/perf/fsl_imx8_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> > @@ -28,6 +28,8 @@
> >  #define CNTL_CLEAR_MASK              0xFFFFFFFD
> >  #define CNTL_OVER_MASK               0xFFFFFFFE
> >
> > +#define CNTL_CP_SHIFT                16
> > +#define CNTL_CP_MASK         (0xFF << CNTL_CP_SHIFT)
> >  #define CNTL_CSV_SHIFT               24
> >  #define CNTL_CSV_MASK                (0xFFU << CNTL_CSV_SHIFT)
> >
> > @@ -427,6 +429,19 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
> >               writel(0, pmu->base + reg);
> >               val = CNTL_EN | CNTL_CLEAR;
> >               val |= FIELD_PREP(CNTL_CSV_MASK, config);
> > +
> > +             /*
> > +              * Workaround for i.MX8MP:
> > +              * Common counters and byte counters share the same COUNTER_CNTL,
> > +              * and byte counters could overflow before cycle counter. Need set
> > +              * counter parameter(CP) of cycle counter to give it initial value
> > +              * which can speed up cycle counter overflow frequency.
> > +              */
> 
> From the comments on path 2, it sounds like this "counter parameter" sets bits
> [31..28] of the counter value, is that correct?

Correct.

> 
> Assuming so, could we please update this comment to say:
> 
>         /*
>          * On i.MX8MP we need to bias the cycle counter to overflow more often.
>          * We do this by initializing bits [31:28] of the counter value via the
>          * COUNTER_CTRL Counter Parameter (CP) field.
>          *
>          * See ddr_perf_counter_enable() for more details.
>          */

Sure, I will update the comment like this.

Thanks,
Xu Yang

> 
> Thanks,
> Mark.
> 
> > +             if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
> > +                     if (counter == EVENT_CYCLES_COUNTER)
> > +                             val |= FIELD_PREP(CNTL_CP_MASK, 0xf0);
> > +             }
> > +
> >               writel(val, pmu->base + reg);
> >       } else {
> >               /* Disable counter */
> > --
> > 2.34.1
> >

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RE: [EXT] Re: [PATCH v2 2/3] perf/imx_ddr: adjust counter result after read cycle counter

[Xu Yang]

Hi Mark,

> On Thu, Jul 13, 2023 at 06:37:57PM +0800, Xu Yang wrote:
> > Because we initialize CP filed to shorten counter0 overflow time, the cycle
> > counter will start couting from a fixed/base value each time. We need to
> > remove the base from the result too. Therefore, we could get precise result
> > from cycle counter.
> 
> This means that patch 1 is incomplete; please fold this into patch 1.

Okay.

> 
> >
> > Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> >
> > ---
> > Changes in v2:
> >  - improve if condition
> > ---
> >  drivers/perf/fsl_imx8_ddr_perf.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
> > index 039069756bbc..d65200d4e96e 100644
> > --- a/drivers/perf/fsl_imx8_ddr_perf.c
> > +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> > @@ -481,6 +481,12 @@ static void ddr_perf_event_update(struct perf_event *event)
> >       int ret;
> >
> >       new_raw_count = ddr_perf_read_counter(pmu, counter);
> > +     /* Workaround for i.MX8MP */
> > +     if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
> > +             if (counter == EVENT_CYCLES_COUNTER)
> > +                     new_raw_count -= 0xF0000000;
> > +     }
> 
> I think as Frank suggested, it would be clearer to have a mask, and I think
> this should have a comment:

Agree, I'm going to update the code as following too.

Thanks,
Xu Yang

> 
>         /*
>          * Remove the bias applied in ddr_perf_counter_enable().
>          */
>         if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) {
>                 if (counter == EVENT_CYCLES_COUNTER)
>                         new_raw_count &= 0x0fffffff;
>         }
> 
> Thanks,
> Mark.
> 
> > +
> >       local64_add(new_raw_count, &event->count);
> >
> >       /*
> > --
> > 2.34.1
> >

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