From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5DD73C0015E for ; Fri, 28 Jul 2023 13:37:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jbBwuaF/FIA8Bmti6Q/JaXDjW9oOit/R8f0GAw/lyDo=; b=VgT8gPfjbx9tub bXwbD8l5aLoLkv9Ap3N2CA8cj9Vaypj4qIKfYYkiBu01jJfvAMjXuGhkoB8Od9MpWe/PAMJif933D iOymxw9mHdFBipwrQazCmirzNf6RvLe0uaNlRvuWSMFscR/ar1f9yMTohU5p6FYmPuFPvVhLOtuTh 8ngzXRwdLkUhlHQzVVBro/9Xy0mEq7b7c/Hy35S49qBt6pKz7aQQ7i9lz826Hb0rVubFCSJ0ly6vA iZ4Q5S40FFbhW/rOT3YSEL89yXrxrTG0A2YlG10XdafUcZzjsMpkv1Pmk846LovWXO8cNl0qFNm94 b+Qf60JdUjM/rMiwcHLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qPNe7-003Y1E-2k; Fri, 28 Jul 2023 13:36:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qPNe4-003Y0j-1d for linux-arm-kernel@lists.infradead.org; Fri, 28 Jul 2023 13:36:42 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ED4932F4; Fri, 28 Jul 2023 06:37:18 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.89.82]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 67BA23F5A1; Fri, 28 Jul 2023 06:36:34 -0700 (PDT) Date: Fri, 28 Jul 2023 14:36:31 +0100 From: Mark Rutland To: Xu Yang Cc: frank.li@nxp.com, will@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/3] perf/imx_ddr: adjust counter result after read cycle counter Message-ID: References: <20230713103758.2627269-1-xu.yang_2@nxp.com> <20230713103758.2627269-2-xu.yang_2@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230713103758.2627269-2-xu.yang_2@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230728_063640_594463_514B769D X-CRM114-Status: GOOD ( 20.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 13, 2023 at 06:37:57PM +0800, Xu Yang wrote: > Because we initialize CP filed to shorten counter0 overflow time, the cycle > counter will start couting from a fixed/base value each time. We need to > remove the base from the result too. Therefore, we could get precise result > from cycle counter. This means that patch 1 is incomplete; please fold this into patch 1. > > Signed-off-by: Xu Yang > > --- > Changes in v2: > - improve if condition > --- > drivers/perf/fsl_imx8_ddr_perf.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c > index 039069756bbc..d65200d4e96e 100644 > --- a/drivers/perf/fsl_imx8_ddr_perf.c > +++ b/drivers/perf/fsl_imx8_ddr_perf.c > @@ -481,6 +481,12 @@ static void ddr_perf_event_update(struct perf_event *event) > int ret; > > new_raw_count = ddr_perf_read_counter(pmu, counter); > + /* Workaround for i.MX8MP */ > + if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { > + if (counter == EVENT_CYCLES_COUNTER) > + new_raw_count -= 0xF0000000; > + } I think as Frank suggested, it would be clearer to have a mask, and I think this should have a comment: /* * Remove the bias applied in ddr_perf_counter_enable(). */ if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { if (counter == EVENT_CYCLES_COUNTER) new_raw_count &= 0x0fffffff; } Thanks, Mark. > + > local64_add(new_raw_count, &event->count); > > /* > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel