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From: Matthew Wilcox <willy@infradead.org>
To: Ian Rogers <irogers@google.com>
Cc: "Alexandre Ghiti" <alexghiti@rivosinc.com>,
	"Brendan Sweeney" <brs@rivosinc.com>,
	"Palmer Dabbelt" <palmer@rivosinc.com>,
	"Jonathan Corbet" <corbet@lwn.net>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Arnaldo Carvalho de Melo" <acme@kernel.org>,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
	"Jiri Olsa" <jolsa@kernel.org>,
	"Namhyung Kim" <namhyung@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Albert Ou" <aou@eecs.berkeley.edu>,
	"Atish Patra" <atishp@atishpatra.org>,
	"Anup Patel" <anup@brainfault.org>,
	"Will Deacon" <will@kernel.org>, "Rob Herring" <robh@kernel.org>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Rémi Denis-Courmont" <remi@remlab.net>,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	"Atish Patra" <atishp@rivosinc.com>
Subject: Re: [PATCH v4 09/10] tools: lib: perf: Implement riscv mmap support
Date: Mon, 31 Jul 2023 20:47:54 +0100	[thread overview]
Message-ID: <ZMgP6hhD/k7QNQ3t@casper.infradead.org> (raw)
In-Reply-To: <CAP-5=fUbiaVwSAhTbymyhdUPcVAXHiQZZexAOnrqid0LsPmfpw@mail.gmail.com>

On Mon, Jul 31, 2023 at 09:46:07AM -0700, Ian Rogers wrote:
> On Mon, Jul 31, 2023 at 9:06 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > I have just had the answer internally (thanks to @Brendan Sweeney):
> > csr modifications can alter how the memory is accessed (satp which
> > changes the address space, sum which allows/disallows userspace
> > access...), so we need the memory barrier to make sure the compiler
> > does not reorder the memory accesses.
> 
> The conditions you mention shouldn't apply here though? Even if you
> add a memory barrier for the compiler what is stopping the hardware
> reordering loads and stores? If it absolutely has to be there then a
> comment something like "There is a bug is riscv where the csrr
> instruction can clobber memory breaking future reads and some how this
> constraint fixes it by ... ".

If the hardware doesn't know that writing to a csr can change how memory
accesses are done and reorders memory accesses around that csr write,
you've got a really broken piece of hardware on your hands ...

I know nothing about risc-v, and maybe the definition says that you need
to put a memory barrier before and/or after it in the instruction stream,
but on all hardware I'm familiar with, writing to a CSR is an implicitly
serialising operation.

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  reply	other threads:[~2023-07-31 19:48 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-27 14:14 [PATCH v4 00/10] riscv: Allow userspace to directly access perf counters Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 01/10] perf: Fix wrong comment about default event_idx Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 02/10] include: riscv: Fix wrong include guard in riscv_pmu.h Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 03/10] riscv: Make legacy counter enum match the HW numbering Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 04/10] drivers: perf: Rename riscv pmu sbi driver Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 05/10] riscv: Prepare for user-space perf event mmap support Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 06/10] drivers: perf: Implement perf event mmap support in the legacy backend Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 07/10] drivers: perf: Implement perf event mmap support in the SBI backend Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 08/10] Documentation: admin-guide: Add riscv sysctl_perf_user_access Alexandre Ghiti
2023-07-27 14:14 ` [PATCH v4 09/10] tools: lib: perf: Implement riscv mmap support Alexandre Ghiti
2023-07-28 17:52   ` Ian Rogers
2023-07-31 10:15     ` Alexandre Ghiti
2023-07-31 10:27       ` Alexandre Ghiti
2023-07-31 15:10         ` Ian Rogers
2023-07-31 16:06           ` Alexandre Ghiti
2023-07-31 16:46             ` Ian Rogers
2023-07-31 19:47               ` Matthew Wilcox [this message]
2023-07-31 21:07                 ` Jessica Clarke
2023-08-01  7:09               ` Alexandre Ghiti
2023-07-31 19:37             ` Jessica Clarke
2023-07-27 14:14 ` [PATCH v4 10/10] perf: tests: Adapt mmap-basic.c for riscv Alexandre Ghiti
2023-07-28 17:54   ` Ian Rogers
2023-07-29  7:38     ` Andrew Jones
  -- strict thread matches above, loose matches on Subject: below --
2023-07-03 12:46 [PATCH v4 00/10] riscv: Allow userspace to directly access perf counters Alexandre Ghiti
2023-07-03 12:46 ` [PATCH v4 09/10] tools: lib: perf: Implement riscv mmap support Alexandre Ghiti
2023-07-14  9:29   ` Atish Patra

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