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Fri, 18 Aug 2023 10:18:51 -0700 Date: Fri, 18 Aug 2023 10:18:50 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , Subject: Re: [PATCH v2] iommu/arm-smmu-v3: Add a user-configurable tlb_invalidate_threshold Message-ID: References: <20230816204350.29150-1-nicolinc@nvidia.com> <20230818161119.GA16216@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230818161119.GA16216@willie-the-truck> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|LV3PR12MB9235:EE_ X-MS-Office365-Filtering-Correlation-Id: 0765e992-4b8e-4d02-dcf6-08dba00f3c12 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CvrUHh9LB1h4B5CyJN9r+rUuUiYxX41ZKSfPQoK8C+1yLeiRbRN44Trw6eeG1o2XlgJv3yhNFmDjMhsN4MTiSnxdtswz1cb2hF5yAk8dChiYF0ycEVJyGeEk7GGv/VM00Yr+Y3Pm/Q5Fw1zJEUuV25xAJbkxLhWlPZI8xBpZVrBjAocpftckCbvwqGru4tGNtANOcgvjJPJxJdXGJe722I4I6seneAjf1gVRQyZv04Qu5d3jwg/ZCtDwCbajay4ROYaS8CtmMbDM818x7RRGQS2/ZoCTpSSVrF2Vzhp56NvPgopj6dALGZHbdAhFucp37oYofFD6PRNt5hFuVWbKAKFPdsu///uEotYxcPORDekSpuVYOV/muQ268NZqt9d6IYoKyXNCReoXvd3niRgi5dAXYh/qPZ9v6fmtYxb5ObRzV0vOBTxRg+xvQqNd9TivRxSk5HRQRWaPJxRQghNwKQ0mHTHou6uVUsSissx0YERcyCdd4WHfR4mUu/o4PVspqViPnto0R1w29Ioz3jDi0WIDU10Zcr1EnPNgqy0S5j08EyvlnhUA/yx3bQ+s0moNr7d+BJn7xPjCIr6aXJKSzYs1SPzZD/gtddG1w7Sm4e6QzAY/UFQA559bKOdDtwJcGl/TpCuKClJ0qrzUg3pWs+zAg7NOS2C0lS8B+5a+RqQy/gH5UknchWkriMC07RiCy/I3iqPVxuWrVowJMy000SnV6o2utlVVXlJm4TSNGU3kdMO2zm8cogkcvpMK6JBs X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(39860400002)(346002)(376002)(186009)(451199024)(82310400011)(1800799009)(36840700001)(46966006)(40470700004)(2906002)(40460700003)(83380400001)(26005)(86362001)(40480700001)(478600001)(336012)(426003)(9686003)(55016003)(5660300002)(41300700001)(36860700001)(70586007)(82740400003)(7636003)(356005)(54906003)(70206006)(316002)(6916009)(4326008)(8936002)(8676002)(33716001)(47076005);DIR:OUT;SFP:1101; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 18, 2023 at 05:11:19PM +0100, Will Deacon wrote: > On Thu, Aug 17, 2023 at 11:36:18AM -0700, Nicolin Chen wrote: > > On Wed, Aug 16, 2023 at 01:43:50PM -0700, Nicolin Chen wrote: > > > > > When receiving an __arm_smmu_tlb_inv_range() call with a large size, there > > > could be a long latency at this function call: one part is coming from a > > > large software overhead in the routine of building commands, and the other > > > part is coming from CMDQ hardware consuming the large number of commands. > > > This latency could be significantly large on an SMMU that does not support > > > range invalidation commands, i.e. no ARM_SMMU_FEAT_RANGE_INV. > > > > > > One way to optimize this is to replace a large number of VA invalidation > > > commands with one single per-asid invalidation command, when the requested > > > size reaches a threshold. This threshold can be configurable depending on > > > the SMMU implementaion. > > > > I'm rethinking about this size-based threshold, since what really > > affects the latency is the number of the invalidation commands in > > the request. So having an npages-based threshold might be optimal, > > though the idea and implementation would be similar. > > On the CPU side, we just have: > > #define MAX_TLBI_OPS PTRS_PER_PTE > > in asm/tlbflush.h > > Can we start off with something similar for the SMMU? I'm not massively > keen on exposing this as a knob to userspace, because I don't think most > people will have a clue about how to tune it. Yes! I was hesitating about an arbitrary threshold setup that actually fits our situation better. Now it makes sense. Thanks for the input! What I would do was to pick a number based on our test results. Yet, it seems that 1024 was chosen at the beginning to fix a softlock bug, and it changed to PTRS_PER_PTE for a better perf, IIUIC. Should we use the similar setup for SMMU? I found it is stored in data->bits_per_level, so perhaps pass it back to the driver via "struct io_pgtable_cfg". Nicolin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel