From: Nicolin Chen <nicolinc@nvidia.com>
To: <will@kernel.org>, <robin.murphy@arm.com>, <jgg@nvidia.com>
Cc: <joro@8bytes.org>, <jean-philippe@linaro.org>,
<apopple@nvidia.com>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>
Subject: Re: [PATCH v2] iommu/arm-smmu-v3: Add a user-configurable tlb_invalidate_threshold
Date: Thu, 17 Aug 2023 11:36:18 -0700 [thread overview]
Message-ID: <ZN5oojF6vKOKB/eI@Asurada-Nvidia> (raw)
In-Reply-To: <20230816204350.29150-1-nicolinc@nvidia.com>
On Wed, Aug 16, 2023 at 01:43:50PM -0700, Nicolin Chen wrote:
> When receiving an __arm_smmu_tlb_inv_range() call with a large size, there
> could be a long latency at this function call: one part is coming from a
> large software overhead in the routine of building commands, and the other
> part is coming from CMDQ hardware consuming the large number of commands.
> This latency could be significantly large on an SMMU that does not support
> range invalidation commands, i.e. no ARM_SMMU_FEAT_RANGE_INV.
>
> One way to optimize this is to replace a large number of VA invalidation
> commands with one single per-asid invalidation command, when the requested
> size reaches a threshold. This threshold can be configurable depending on
> the SMMU implementaion.
I'm rethinking about this size-based threshold, since what really
affects the latency is the number of the invalidation commands in
the request. So having an npages-based threshold might be optimal,
though the idea and implementation would be similar.
Thanks
Nicolin
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next prev parent reply other threads:[~2023-08-17 18:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-16 20:43 [PATCH v2] iommu/arm-smmu-v3: Add a user-configurable tlb_invalidate_threshold Nicolin Chen
2023-08-17 18:36 ` Nicolin Chen [this message]
2023-08-18 16:11 ` Will Deacon
2023-08-18 17:18 ` Nicolin Chen
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