From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76111EE4996 for ; Tue, 22 Aug 2023 09:02:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OtVsy6wcdaBZVBYeZJTA0/puT5DpJK8/aSV2T7CB9+0=; b=X0RHuusQYImjLQ kXpHdSNXy1UJckNTpAgNCG6l1nctylmcSoCOhcEm2LgJ2FKZgH+KmaJPEA0cL7EuyXezQhbDZrjch iSx6pCx3eZmlzV1ZDkKX+SCz7uuXWJWVLVZSgui8yeNDGnqylDK9oVk3vOuHmJhnXBW6F9ZxH2Ks9 IeaA4JnLG4gIbs745jLXeo9yC1+VE6QEtHtTGsYwH4Uk11wkoXvxI6yyEyRdU0hHfyusimUx8sVvT bYW6N3Lu7oTvNdgC7f5tO8OsxipIGHl/cBNr+g3d4g+r9KKWSitMRCH7HtpwfEt5jTDtGvnL68RI7 huHXuW5q8o1DM5HxpuXQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qYNHN-00FWi9-14; Tue, 22 Aug 2023 09:02:25 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qYNHJ-00FWgY-38 for linux-arm-kernel@lists.infradead.org; Tue, 22 Aug 2023 09:02:23 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C9F3C63ACD; Tue, 22 Aug 2023 09:02:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 281D1C433C7; Tue, 22 Aug 2023 09:02:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692694940; bh=54luh6aWDj+Dj6PCgagvuO1k+5MIOroKY5M7KCBKnsw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=I5NWbbQmafaI/unLPzRx2CDciEoxctCBCvzlAgz2f0THOSfkd6gFdWSKEx3ZHmox6 5g3aIfJgb3li19UAfb41tbDKfwnxVn6OD3bvIkx085TRPEm11sXWYz0q76RKDkeuWs 86CsYc8qV+tXfj7ANzydP9E+9I0kYqVrVqgwIm+45ZCW6Cnt5H39EZvuwxgLWm1nCx ZOJMiLxNlYz/FdtelyeoXu5MrT3FQSTCDJ3/avpHrmhjoId5hs7Qm6vMTcAa0nC5tB mF3+KyKwPhMuyutmf2nDVDS2u+TcQDfdyRA8n7g7BW89aAeeeEMNcWmWUZ4z75xu68 Tb828Ha8kERMQ== Date: Tue, 22 Aug 2023 11:02:11 +0200 From: Lorenzo Pieralisi To: Frank Li Cc: bhelgaas@google.com, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com, helgaas@kernel.org, imx@lists.linux.dev, kw@linux.com, leoyang.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lorenzo.pieralisi@arm.com, mani@kernel.org, manivannan.sadhasivam@linaro.org, minghuan.lian@nxp.com, mingkai.hu@nxp.com, robh+dt@kernel.org, roy.zang@nxp.com, shawnguo@kernel.org, zhiqiang.hou@nxp.com Subject: Re: [PATCH v12 3/3] PCI: layerscape: Add power management support for ls1028a Message-ID: References: <20230821184815.2167131-1-Frank.Li@nxp.com> <20230821184815.2167131-4-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230821184815.2167131-4-Frank.Li@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230822_020222_117759_AB708269 X-CRM114-Status: GOOD ( 29.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 21, 2023 at 02:48:15PM -0400, Frank Li wrote: > From: Hou Zhiqiang > > Add PME_Turn_off/PME_TO_Ack handshake sequence for ls1028a platform. Call > common dwc dw_pcie_suspend(resume)_noirq() function when system enter/exit > suspend state. > > Acked-by: Manivannan Sadhasivam > Signed-off-by: Hou Zhiqiang > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-layerscape.c | 135 ++++++++++++++++++-- > 1 file changed, 126 insertions(+), 9 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > index ed5fb492fe08..97b8d3329df7 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape.c > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > @@ -8,9 +8,11 @@ > * Author: Minghuan Lian > */ > > +#include > #include > #include > #include > +#include > #include > #include > #include > @@ -20,6 +22,7 @@ > #include > #include > > +#include "../../pci.h" > #include "pcie-designware.h" > > /* PEX Internal Configuration Registers */ > @@ -27,12 +30,26 @@ > #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ > #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */ > > +/* PF Message Command Register */ > +#define LS_PCIE_PF_MCR 0x2c > +#define PF_MCR_PTOMR BIT(0) > +#define PF_MCR_EXL2S BIT(1) > + > #define PCIE_IATU_NUM 6 > > +struct ls_pcie_drvdata { > + const u32 pf_off; > + bool pm_support; > +}; > + > struct ls_pcie { > struct dw_pcie *pci; > + const struct ls_pcie_drvdata *drvdata; > + void __iomem *pf_base; > + bool big_endian; > }; > > +#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) > #define to_ls_pcie(x) dev_get_drvdata((x)->dev) > > static bool ls_pcie_is_bridge(struct ls_pcie *pcie) > @@ -73,6 +90,64 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) > iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); > } > > +static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) > +{ > + if (pcie->big_endian) > + return ioread32be(pcie->pf_base + off); > + > + return ioread32(pcie->pf_base + off); > +} > + > +static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) > +{ > + if (pcie->big_endian) > + iowrite32be(val, pcie->pf_base + off); > + else > + iowrite32(val, pcie->pf_base + off); > +} > + > +static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + u32 val; > + int ret; > + > + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); > + val |= PF_MCR_PTOMR; > + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); > + > + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, > + val, !(val & PF_MCR_PTOMR), > + PCIE_PME_TO_L2_TIMEOUT_US/10, > + PCIE_PME_TO_L2_TIMEOUT_US); > + if (ret) > + dev_err(pcie->pci->dev, "PME_Turn_off timeout\n"); > +} > + > +static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct ls_pcie *pcie = to_ls_pcie(pci); > + u32 val; > + int ret; > + > + /* > + * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link > + * to exit L2 state. > + */ > + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); > + val |= PF_MCR_EXL2S; > + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); > + > + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, > + val, !(val & PF_MCR_EXL2S), > + 1000, > + 10000); I can add a comment myself - please explain how this delay was chosen, any piece of information could be useful for a future developer, let me know and I will add it. > + if (ret) > + dev_err(pcie->pci->dev, "L2 exit timeout\n"); > +} > + > static int ls_pcie_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -91,18 +166,27 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) > > static const struct dw_pcie_host_ops ls_pcie_host_ops = { > .host_init = ls_pcie_host_init, > + .pme_turn_off = ls_pcie_send_turnoff_msg, > +}; > + > +static const struct ls_pcie_drvdata ls1021a_drvdata = { I suggest adding .pm_support = false explicitly here, I can do it myself. Thanks, Lorenzo > +}; > + > +static const struct ls_pcie_drvdata layerscape_drvdata = { > + .pf_off = 0xc0000, > + .pm_support = true, > }; > > static const struct of_device_id ls_pcie_of_match[] = { > - { .compatible = "fsl,ls1012a-pcie", }, > - { .compatible = "fsl,ls1021a-pcie", }, > - { .compatible = "fsl,ls1028a-pcie", }, > - { .compatible = "fsl,ls1043a-pcie", }, > - { .compatible = "fsl,ls1046a-pcie", }, > - { .compatible = "fsl,ls2080a-pcie", }, > - { .compatible = "fsl,ls2085a-pcie", }, > - { .compatible = "fsl,ls2088a-pcie", }, > - { .compatible = "fsl,ls1088a-pcie", }, > + { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, > + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, > + { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, > + { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, > + { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, > + { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, > + { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, > + { .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata }, > + { .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata }, > { }, > }; > > @@ -121,6 +205,8 @@ static int ls_pcie_probe(struct platform_device *pdev) > if (!pci) > return -ENOMEM; > > + pcie->drvdata = of_device_get_match_data(dev); > + > pci->dev = dev; > pci->pp.ops = &ls_pcie_host_ops; > > @@ -131,6 +217,10 @@ static int ls_pcie_probe(struct platform_device *pdev) > if (IS_ERR(pci->dbi_base)) > return PTR_ERR(pci->dbi_base); > > + pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); > + > + pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; > + > if (!ls_pcie_is_bridge(pcie)) > return -ENODEV; > > @@ -139,12 +229,39 @@ static int ls_pcie_probe(struct platform_device *pdev) > return dw_pcie_host_init(&pci->pp); > } > > +static int ls_pcie_suspend_noirq(struct device *dev) > +{ > + struct ls_pcie *pcie = dev_get_drvdata(dev); > + > + if (!pcie->drvdata->pm_support) > + return 0; > + > + return dw_pcie_suspend_noirq(pcie->pci); > +} > + > +static int ls_pcie_resume_noirq(struct device *dev) > +{ > + struct ls_pcie *pcie = dev_get_drvdata(dev); > + > + if (!pcie->drvdata->pm_support) > + return 0; > + > + ls_pcie_exit_from_l2(&pcie->pci->pp); > + > + return dw_pcie_resume_noirq(pcie->pci); > +} > + > +static const struct dev_pm_ops ls_pcie_pm_ops = { > + NOIRQ_SYSTEM_SLEEP_PM_OPS(ls_pcie_suspend_noirq, ls_pcie_resume_noirq) > +}; > + > static struct platform_driver ls_pcie_driver = { > .probe = ls_pcie_probe, > .driver = { > .name = "layerscape-pcie", > .of_match_table = ls_pcie_of_match, > .suppress_bind_attrs = true, > + .pm = &ls_pcie_pm_ops, > }, > }; > builtin_platform_driver(ls_pcie_driver); > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel