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b=s3QAcRz5pHayE+Km2AtBpMf8EhBY2b4mtvkXbYR9y22Oso1Rn97Ub940VCPQioqzS P2acX6JMW6HkR3/xoHozZAMjzeyBwg0lvzEYRt4QSLsM7Z6LoDJBK61rFr/DWPaH6h SHoSyKmkyGgE1Afy3zRKNUlb7GFBwr9iHebXzL2eaU6MMR+rfOOpqOozUyA6CpQyr9 RZ34lx+CbY09ksmw15SdkzOk3zfRl+so22kC0gicp50cS9HNpJs2BlGUnvE+tHUhbH z+9dy75OiqkolsEDG4MXj3UGhtidzJp7dhGi/7b1heZSiMG/Z+biFSXjLC/UBuh0x4 E/Zp7YgJ1oKvg== Date: Wed, 6 Sep 2023 13:27:43 +0200 From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Mark Rutland , Robin Murphy , Rob Herring , Fang Xiang , Marc Zyngier Subject: Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property Message-ID: References: <20230905104721.52199-1-lpieralisi@kernel.org> <20230906094139.16032-1-lpieralisi@kernel.org> <20230906094139.16032-2-lpieralisi@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230906094139.16032-2-lpieralisi@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230906_042750_223350_D8705013 X-CRM114-Status: GOOD ( 19.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 06, 2023 at 11:41:38AM +0200, Lorenzo Pieralisi wrote: > The GIC v3 specifications allow redistributors and ITSes interconnect > ports used to access memory to be wired up in a way that makes the > respective initiators/memory observers non-coherent. > > Add the standard dma-noncoherent property to the GICv3 bindings to > allow firmware to describe the redistributors/ITSes components and > interconnect ports behaviour in system designs where the redistributors > and ITSes are not coherent with the CPU. > > Signed-off-by: Lorenzo Pieralisi > Cc: Rob Herring > --- > .../bindings/interrupt-controller/arm,gic-v3.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > index 39e64c7f6360..c9bc9aad93f1 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > @@ -106,6 +106,12 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint32 > maximum: 4096 > > + dma-noncoherent: > + description: > + Present if the GIC redistributors permit programming shareability > + and cacheability attributes but are connected to a non-coherent > + downstream interconnect. > + > msi-controller: > description: > Only present if the Message Based Interrupt functionality is > @@ -193,6 +199,12 @@ patternProperties: > compatible: > const: arm,gic-v3-its > > + dma-noncoherent: > + description: > + Present if the GIC ITS permits programming shareability and > + cacheability attributes but are connected to a non-coherent s/are/is Sorry, I will update the patch accordingly. Lorenzo > + downstream interconnect. > + > msi-controller: true > > "#msi-cells": > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel