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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 04-10-23, 23:03, Laurent Pinchart wrote: > On Wed, Oct 04, 2023 at 07:21:00PM +0530, Vinod Koul wrote: > > On 29-08-23, 18:55, Laurent Pinchart wrote: > > > Hi Jai, > > > > > > (CC'ing Vinod, the maintainer of the DMA engine subsystem, for a > > > question below) > > > > Sorry this got lost > > No worries. > > > > On Fri, Aug 18, 2023 at 03:55:06PM +0530, Jai Luthra wrote: > > > > On Aug 15, 2023 at 16:00:51 +0300, Tomi Valkeinen wrote: > > > > > On 11/08/2023 13:47, Jai Luthra wrote: > > > > > > From: Pratyush Yadav > > > > > > [snip] > > > > > > > > > +static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count) > > > > > > +{ > > > > > > + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); > > > > > > + struct ti_csi2rx_dma *dma = &csi->dma; > > > > > > + struct ti_csi2rx_buffer *buf; > > > > > > + unsigned long flags; > > > > > > + int ret = 0; > > > > > > + > > > > > > + spin_lock_irqsave(&dma->lock, flags); > > > > > > + if (list_empty(&dma->queue)) > > > > > > + ret = -EIO; > > > > > > + spin_unlock_irqrestore(&dma->lock, flags); > > > > > > + if (ret) > > > > > > + return ret; > > > > > > + > > > > > > + dma->drain.len = csi->v_fmt.fmt.pix.sizeimage; > > > > > > + dma->drain.vaddr = dma_alloc_coherent(csi->dev, dma->drain.len, > > > > > > + &dma->drain.paddr, GFP_KERNEL); > > > > > > + if (!dma->drain.vaddr) > > > > > > + return -ENOMEM; > > > > > > > > > > This is still allocating a large buffer every time streaming is started (and > > > > > with streams support, a separate buffer for each stream?). > > > > > > > > > > Did you check if the TI DMA can do writes to a constant address? That would > > > > > be the best option, as then the whole buffer allocation problem goes away. > > > > > > > > I checked with Vignesh, the hardware can support a scenario where we > > > > flush out all the data without allocating a buffer, but I couldn't find > > > > a way to signal that via the current dmaengine framework APIs. Will look > > > > into it further as it will be important for multi-stream support. > > > > > > That would be the best option. It's not immediately apparent to me if > > > the DMA engine API supports such a use case. > > > dmaengine_prep_interleaved_dma() gives you finer grain control on the > > > source and destination increments, but I haven't seen a way to instruct > > > the DMA engine to direct writes to /dev/null (so to speak). Vinod, is > > > this something that is supported, or could be supported ? > > > > Write to a dummy buffer could have the same behaviour, no? > > Yes, but if the DMA engine can write to /dev/null, that avoids > allocating a dummy buffer, which is nicer. For video use cases, dummy > buffers are often large. hmmm maybe I haven't comprehended it full, would you mind explaining the details on how such a potential interleaved transfer would look like so that we can model it or change apis to model this -- ~Vinod _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel