From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32176CDB47E for ; Thu, 12 Oct 2023 09:25:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sFqyBXlz4zXD/EhpmaJCCWfubI43rRz0tHF6/bbJvRc=; b=c3pQyAQn0o4Jib dhzjhd8Pzu/gtiRTKS5fKB1PvQMv/Ejy9rg6PpkBBfAIVkGGqqKGSdwwqOKzJGJYWC0bmUM0bdwH8 SlbU4dSutFUwa+6jtQgY/090W0cza4Q6yA9usLIejoAEEu/2cV3DG5qudBEwI5UUgen/0x8Kjrn+W h0twLFbeJ6F80rfc8Ucu4WWjHa9WYzHrwpUrj+fhiMLvEX1UomuHjFyyNsX0fGirF3Hb05fb3nH8Q TfaLM7dzn3dMi+kEjONqr+Kb69xbZtqkVD/UYHI5yTLh5vE3FGLiI1eEVaD06z/XTfXmfXlE1gCH7 6nTtfGaFYUKbKe9XZMhg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qqrw8-000N2P-0j; Thu, 12 Oct 2023 09:24:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qqrw5-000N1l-1Y for linux-arm-kernel@lists.infradead.org; Thu, 12 Oct 2023 09:24:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E7DB13D5; Thu, 12 Oct 2023 02:25:31 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.81.67]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6CD6A3F762; Thu, 12 Oct 2023 02:24:49 -0700 (PDT) Date: Thu, 12 Oct 2023 10:24:46 +0100 From: Mark Rutland To: James Clark Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, zhangshaokun@hisilicon.com, Will Deacon , linux-kernel@vger.kernel.org Subject: Re: [PATCH] driver: perf: arm_pmuv3: Read PMMIR_EL1 unconditionally Message-ID: References: <20231009075631.193208-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231012_022453_569522_5D2194B1 X-CRM114-Status: GOOD ( 28.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Oct 09, 2023 at 09:59:19AM +0100, James Clark wrote: > On 09/10/2023 08:56, Anshuman Khandual wrote: > > PMMIR_EL1 needs to be captured in 'armpmu->reg_pmmir', for all appropriate > > PMU version implementations where the register is available and reading it > > is valid . Hence checking for bus slot event presence is redundant and can > > be dropped. > > > > Cc: Will Deacon > > Cc: Mark Rutland > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > Signed-off-by: Anshuman Khandual > > --- > > This applies on v6.6-rc5. > > > > drivers/perf/arm_pmuv3.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > > index 1e72b486c033..9fc1b6da5106 100644 > > --- a/drivers/perf/arm_pmuv3.c > > +++ b/drivers/perf/arm_pmuv3.c > > @@ -1129,7 +1129,7 @@ static void __armv8pmu_probe_pmu(void *info) > > pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS); > > > > /* store PMMIR register for sysfs */ > > - if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31))) > > + if (is_pmuv3p4(pmuver)) > > cpu_pmu->reg_pmmir = read_pmmir(); > > else > > cpu_pmu->reg_pmmir = 0; > > > This does have the side effect of showing non-zero values in caps/slots > even when the STALL_SLOT event isn't implemented. I think that's the > scenario that the original commit (f5be3a61fd) was trying to avoid: > > /sys/bus/event_source/devices/armv8_pmuv3_0/caps/slots is exposed > under sysfs. [If] Both ARMv8.4-PMU and STALL_SLOT event are > implemented, it returns the slots from PMMIR_EL1, otherwise it will > return 0. We check for the STALL_SLOT event becuase (at the time) the ARM ARM said: | If STALL_SLOT is not implemented, it is IMPLEMENTATION DEFINED whether the | PMMIR System registers are implemented. ... and this was necessary to avoid triggering an UNDEFINED exception if we attempted to read PMMIR on a CPU which didn't actually implement it. See: https://lore.kernel.org/linux-arm-kernel/20200720101518.GA11516@willie-the-truck/ https://lore.kernel.org/linux-arm-kernel/20200720105019.GA54220@C02TD0UTHF1T.local/ https://lore.kernel.org/linux-arm-kernel/20200720105410.GD11516@willie-the-truck/ As I promised in that thread, I did raise that with our architects. According to the bug I filed against the architecture, this was tightened such that ARMv8.4-PMU gauaranteed the presence of PMMIR, and that should have changed between the G.a and G.b releases of the ARM ARM. Anshuman, can you go and check that the wording did chaange between G.a and G.b? Assuming it did (and the wording in the latest J.a release is also fine), please update the commit message to describe the history above. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel