From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56C59CDB47E for ; Fri, 13 Oct 2023 14:57:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lNT88SeBaf6zTLeGjeZfgGDUiI3dZAv1uLNDwdaO98Y=; b=J1J3VI0groPoYz vmIUCOL1wdwEWFMDGnEu+MMyNmCwESmIFdn7ApSyk4p3AIPfp/sS/vHmPBw//Ng9Q/o/Z9S0bcw/H Repat0yOuO3iByl0SmQQ076QVVEvaFsdbBUdVb0Oh104shZuha2jXoPzY5is+6uRMvEVj2BK0kJzQ 6qjfwRHRX8qpVDbgyKaIkmc8Vl++eQn7mW4O2bmXuyodssIjjWlRYVSPJXKcTRikqUVWghKEg50Xp wWV2m9mcQdwQc5cu2eBjQKfxXXjpP/pnMuMOUXraFSwykxs5mrg995MVupXna4tEDsN7oeN5myO4U CRPjlOrmsggjERdxTJ0Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qrJbN-003ctD-2f; Fri, 13 Oct 2023 14:57:21 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qrJbJ-003csC-2G for linux-arm-kernel@lists.infradead.org; Fri, 13 Oct 2023 14:57:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81B9611FB; Fri, 13 Oct 2023 07:57:50 -0700 (PDT) Received: from localhost (ionvoi01-desktop.cambridge.arm.com [10.2.78.69]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AD6313F7A6; Fri, 13 Oct 2023 07:57:09 -0700 (PDT) Date: Fri, 13 Oct 2023 15:57:08 +0100 From: Ionela Voinescu To: Jeremy Linton Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: cpufeature: Display the set of cores with a feature Message-ID: References: <20231013013016.197102-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231013013016.197102-1-jeremy.linton@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231013_075717_857221_E7815F1B X-CRM114-Status: GOOD ( 30.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Thursday 12 Oct 2023 at 20:30:16 (-0500), Jeremy Linton wrote: > The AMU feature can be enabled on a subset of the cores in a system. > Because of that, it prints a message for each core as it is detected. > This becomes tedious when there are hundreds of cores. Instead, for > CPU features which can be enabled on a subset of the present cores, > lets wait until update_cpu_capabilities() and print the subset of cores > the feature was enabled on. > > Signed-off-by: Jeremy Linton > --- > arch/arm64/include/asm/cpufeature.h | 2 ++ > arch/arm64/kernel/cpufeature.c | 16 +++++++++++++--- > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 5bba39376055..19b4d001d845 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -23,6 +23,7 @@ > #include > #include > #include > +#include > > /* > * CPU feature register tracking > @@ -380,6 +381,7 @@ struct arm64_cpu_capabilities { > * method is robust against being called multiple times. > */ > const struct arm64_cpu_capabilities *match_list; > + const struct cpumask *cpus; > }; > > static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap) > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 444a73c2e638..18711e35924c 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1944,8 +1944,6 @@ int get_cpu_with_amu_feat(void) > static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) > { > if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { > - pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", > - smp_processor_id()); > cpumask_set_cpu(smp_processor_id(), &amu_cpus); > > /* 0 reference values signal broken/disabled counters */ > @@ -2411,10 +2409,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > * message to be shown until at least one CPU is detected to > * support the feature. > */ > + .desc = "Activity Monitors Unit (AMU)", > .capability = ARM64_HAS_AMU_EXTN, > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > .matches = has_amu, > .cpu_enable = cpu_amu_enable, > + .cpus = &amu_cpus, > ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) > }, > #endif /* CONFIG_ARM64_AMU_EXTN */ > @@ -2981,7 +2981,7 @@ static void update_cpu_capabilities(u16 scope_mask) > !caps->matches(caps, cpucap_default_scope(caps))) > continue; > > - if (caps->desc) > + if (caps->desc && !caps->cpus) > pr_info("detected: %s\n", caps->desc); > > __set_bit(caps->capability, system_cpucaps); > @@ -3330,6 +3330,7 @@ unsigned long cpu_get_elf_hwcap2(void) > > static void __init setup_system_capabilities(void) > { > + int i; > /* > * We have finalised the system-wide safe feature > * registers, finalise the capabilities that depend > @@ -3338,6 +3339,15 @@ static void __init setup_system_capabilities(void) > */ > update_cpu_capabilities(SCOPE_SYSTEM); > enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); > + > + for (i = 0; i < ARM64_NCAPS; i++) { > + const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; > + > + if (caps && caps->cpus && caps->desc && > + cpumask_any(caps->cpus) < nr_cpu_ids) > + pr_info("detected: %s on CPU%*pbl\n", > + caps->desc, cpumask_pr_args(caps->cpus)); > + } > } > > void __init setup_cpu_features(void) > -- > 2.41.0 > It looks very nice to me! I gave it a run on an RD-N2 FVP so FWIW: Reviewed-by: Ionela Voinescu Tested-by: Ionela Voinescu The same could be used for DBM, but I'm not sure if creating a mask of supporting CPUs is worth it, for this purpose only. Hope it helps, Ionela. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel