From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DE6DC4332F for ; Mon, 30 Oct 2023 07:14:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WmAte2Cl4AK/CXNMFaY7nhrwWVBytLGNVel84D9nP38=; b=CoB5SJvaaaaRxZ wip3BbeDDL8db/Z2uc6JlKcMSs+bQ+1ivhjILncEJh98n0NkavOO5lLRt9cTq0R07FwXWxWGW+C1M 2ZJo19uwYYW/nYNVuaHun7xDupyusLom57VtksSKYZ1OyfJUDdVnqFCC3kJwsh+FXVV/v93Jnr7JC MQZnLV5XVWR99hcuXaPCystuKCosCeHDbSghWOPjbsLkMD3sxzUfB0OUYB2g+GtQRksVvkretWkF0 gE2jvD4EypnuiYXjSkq1AsWQ6oJL7QpIkHKISP1PcAxlT3PAfwF0SdZi+wNqmhMi5w0SvAooJDP3T HiqzHYHP26UsihhuI+sQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qxMTe-002jBv-2c; Mon, 30 Oct 2023 07:14:22 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qxMTb-002jBJ-0s; Mon, 30 Oct 2023 07:14:20 +0000 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 39U7Cl8k048592; Mon, 30 Oct 2023 15:12:47 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from APC323 (10.0.12.98) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 30 Oct 2023 15:12:46 +0800 Date: Mon, 30 Oct 2023 15:12:46 +0800 From: Yu-Chien Peter Lin To: Thomas Gleixner CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [RFC PATCH v3 RESEND 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number Message-ID: References: <20231023004100.2663486-1-peterlin@andestech.com> <20231023004100.2663486-3-peterlin@andestech.com> <87a5s44jyc.ffs@tglx> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87a5s44jyc.ffs@tglx> User-Agent: Mutt/2.2.10 (2023-03-25) X-Originating-IP: [10.0.12.98] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 39U7Cl8k048592 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231030_001419_765722_E860C79E X-CRM114-Status: GOOD ( 19.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Thomas, Thanks for the review. On Fri, Oct 27, 2023 at 09:12:59AM +0200, Thomas Gleixner wrote: > On Mon, Oct 23 2023 at 08:40, Yu Chien Peter Lin wrote: > > Currently, the implementation of the RISC-V INTC driver uses the > > interrupt cause as hwirq and has a limitation of supporting a > > maximum of 64 hwirqs. However, according to the privileged spec, > > interrupt causes >= 16 are defined for platform use. > > > > This limitation prevents us from fully utilizing the available > > local interrupt sources. Additionally, the hwirqs used on RISC-V > > are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf > > or T-Head's PMU irq) being currently used for supervisor mode. > > > > The patch switches to using irq_domain_create_tree() which > > git grep "This patch" Documentation/process/ Sure, will fix. > > creates the radix tree map, allowing us to handle a larger > > number of hwirqs. > > Who is 'us'? We are not part of the chip and please write out 'hardware > interrupts' OK! > > @@ -24,10 +24,8 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) > > { > > unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; > > > > - if (unlikely(cause >= BITS_PER_LONG)) > > - panic("unexpected interrupt cause"); > > - > > - generic_handle_domain_irq(intc_domain, cause); > > + if (generic_handle_domain_irq(intc_domain, cause)) > > + pr_warn("Failed to handle interrupt (cause: %ld)\n", cause); > > pr_warn_once() or at least pr_warn_ratelimited(). OK! > > } > > > > /* > > @@ -117,8 +115,8 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) > > { > > int rc; > > > > - intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, > > - &riscv_intc_domain_ops, NULL); > > + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, > > + NULL); > > Put it into one line. Linebreaking arguments is really only required > when the line length is exceedingly long. This one is not. OK! will fix. Thanks, Peter Lin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel