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From: Oliver Upton To: Marc Zyngier Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: Independently update HDFGRTR_EL2 and HDFGWTR_EL2 Message-ID: References: <20231018030007.1968317-1-anshuman.khandual@arm.com> <86r0lsm7cq.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <86r0lsm7cq.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231018_131620_323155_E38DCEAA X-CRM114-Status: GOOD ( 19.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 18, 2023 at 01:40:37PM +0100, Marc Zyngier wrote: > On Wed, 18 Oct 2023 04:00:07 +0100, > Anshuman Khandual wrote: > > > > Currently PMSNEVFR_EL1 system register read, and write access EL2 traps are > > disabled, via setting the same bit (i.e 62) in HDFGRTR_EL2, and HDFGWTR_EL2 > > respectively. Although very similar, bit fields are not exact same in these > > two EL2 trap configure registers particularly when it comes to read-only or > > write-only accesses such as ready-only 'HDFGRTR_EL2.nBRBIDR' which needs to > > be set while enabling BRBE on NVHE platforms. Using the exact same bit mask > > fields for both these trap register risk writing into their RESERVED areas, > > which is undesirable. > > Sorry, I don't understand at all what you are describing. You seem to > imply that the read and write effects of the FGT doesn't apply the > same way. But my reading of the ARM ARM is that behave completely > symmetrically. nBRBIDR is an asymmetric bit (bit 59 of HDFGWTR_EL2 is RES0). While the architecture *could* repurpose this WTR bit for something else, that feels rather implementation and software hostile. I don't think there's a practical issue here, especially since the architecture has already allocated another pair of debug trap registers to make room for more bits. > So what has changed here, aside from clobbering an extra register? The > masks are the same, the initial values are the same... Is it in > preparation for some other work? Yeah, it feels as though this patch is taken out of context. Without a justifying functional change I don't see the value in fiddling with this code. -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel