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Thu, 19 Oct 2023 12:48:29 +0000 Date: Thu, 19 Oct 2023 14:48:29 +0200 From: Andrea della Porta To: Mark Rutland Cc: Andrea della Porta , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, nik.borisov@suse.com Subject: Re: [PATCH 3/4] arm64/entry-common: Make Aarch32 syscalls' availability depend on aarch32_enabled() Message-ID: Mail-Followup-To: Mark Rutland , Andrea della Porta , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, nik.borisov@suse.com References: <88bdea628a13747bff32c0c3055d6d6ef7264d96.1697614386.git.andrea.porta@suse.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Authentication-Results: smtp-out1.suse.de; none X-Spamd-Result: default: False [-10.60 / 50.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; NEURAL_HAM_LONG(-3.00)[-1.000]; MIME_GOOD(-0.10)[text/plain]; REPLY(-4.00)[]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; NEURAL_HAM_SHORT(-1.00)[-1.000]; RCPT_COUNT_SEVEN(0.00)[7]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; MID_RHS_NOT_FQDN(0.50)[]; RCVD_COUNT_TWO(0.00)[2]; RCVD_TLS_ALL(0.00)[]; BAYES_HAM(-3.00)[100.00%] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231019_054833_972900_49A273E8 X-CRM114-Status: GOOD ( 26.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 13:57 Wed 18 Oct , Mark Rutland wrote: > On Wed, Oct 18, 2023 at 01:13:21PM +0200, Andrea della Porta wrote: > > Another major aspect of supporting running of 32bit processes is the > > ability to access 32bit syscalls. Such syscalls can be invoked by > > using the svc instruction. > > > > If Aarch32 emulation is disabled ensure that calling svc results > > in the same behavior as if CONFIG_COMPAT has not been enabled (i.e. > > a kernel panic). > > It's not "emulation" it's directly supported by the hardware. You're right. I also struggled to use this label but I just reused the same name from Nikolai's patchset for x86, in the hope that the option would be more recognizable (something like 'ARCH_emulation' that could be used maybe for other platforms as well), but I agree with you that this is highly misleading. I will change it to something more straightforward. > > > > > Signed-off-by: Andrea della Porta > > --- > > arch/arm64/kernel/entry-common.c | 25 ++++++++++++++++++++++--- > > 1 file changed, 22 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c > > index 69ff9b8c0bde..32761760d9dd 100644 > > --- a/arch/arm64/kernel/entry-common.c > > +++ b/arch/arm64/kernel/entry-common.c > > @@ -802,6 +802,11 @@ asmlinkage void noinstr el0t_64_error_handler(struct pt_regs *regs) > > } > > > > #ifdef CONFIG_COMPAT > > +UNHANDLED(el0t, 32, sync_ni) > > +UNHANDLED(el0t, 32, irq_ni) > > +UNHANDLED(el0t, 32, fiq_ni) > > +UNHANDLED(el0t, 32, error_ni) > > IRQ, FIQ, and SError are not syscalls, so the commit title is bad. Agreed. I'll call them exceptions. > > > + > > static void noinstr el0_cp15(struct pt_regs *regs, unsigned long esr) > > { > > enter_from_user_mode(regs); > > @@ -821,6 +826,11 @@ static void noinstr el0_svc_compat(struct pt_regs *regs) > > > > asmlinkage void noinstr el0t_32_sync_handler(struct pt_regs *regs) > > { > > + if (!aarch32_enabled()) { > > + el0t_32_sync_ni_handler(regs); > > + return; > > + } > > Why do we have to do this at all? > > If we don't have AArch32 tasks, these paths are unreachable. Why do we need to > check that they aren't called? > > Mark. Agreed. Please see also my previous comments here: https://lore.kernel.org/lkml/ZTEKabxNdegsbxyv@apocalypse/ https://lore.kernel.org/lkml/ZTD0DAes-J-YQ2eu@apocalypse/ but again, that's only speculative as of now, so we can ignore that part. Andrea _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel