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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Conor, On Thu, Oct 19, 2023 at 05:02:18PM +0100, Conor Dooley wrote: > On Thu, Oct 19, 2023 at 10:01:56PM +0800, Yu Chien Peter Lin wrote: > > The Andes PMU extension provides the same mechanism as Sscofpmf, > > allowing us to reuse the SBI PMU driver to support event sampling > > and mode filtering. > > > > To make use of this custom PMU extension, "xandespmu" needs > > to be appended to the riscv,isa-extensions for each cpu node > > in device-tree, and enable CONFIG_ANDES_CUSTOM_PMU. > > > > Signed-off-by: Yu Chien Peter Lin > > Reviewed-by: Charles Ci-Jyun Wu > > Reviewed-by: Leo Yu-Chi Liang > > Co-developed-by: Locus Wei-Han Chen > > Signed-off-by: Locus Wei-Han Chen > > --- > > Changes v1 -> v2: > > - New patch > > --- > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/kernel/cpufeature.c | 1 + > > drivers/perf/Kconfig | 14 ++++++++++++++ > > drivers/perf/riscv_pmu_sbi.c | 35 +++++++++++++++++++++++++++++----- > > 4 files changed, 46 insertions(+), 5 deletions(-) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index d3082391c901..eecfe95d5050 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -59,6 +59,7 @@ > > #define RISCV_ISA_EXT_ZIFENCEI 41 > > #define RISCV_ISA_EXT_ZIHPM 42 > > #define RISCV_ISA_EXT_XTHEADPMU 43 > > +#define RISCV_ISA_EXT_XANDESPMU 44 > > > > #define RISCV_ISA_EXT_MAX 64 > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 4a3fb017026c..a8e71c6dfb3e 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -182,6 +182,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > > __RISCV_ISA_EXT_DATA(xtheadpmu, RISCV_ISA_EXT_XTHEADPMU), > > + __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU), > > This does not following the ordering convention (see the comment above > this datastructure) and is not documented in the dt-binding AFAICT. OK, will insert the xandespmu here. Thanks, Peter Lin > Cheers, > Conor. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel