From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Conor Dooley <conor@kernel.org>
Cc: <acme@kernel.org>, <adrian.hunter@intel.com>,
<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
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Subject: Re: [PATCH v3 00/13] Support Andes PMU extension
Date: Mon, 23 Oct 2023 08:13:10 +0800 [thread overview]
Message-ID: <ZTW6lgK1oifvtqyH@APC323> (raw)
In-Reply-To: <20231022-cabana-crate-503b6e8d0481@spud>
On Sun, Oct 22, 2023 at 07:00:28PM +0100, Conor Dooley wrote:
> Hey,
>
> On Sun, Oct 22, 2023 at 11:18:45PM +0800, Yu Chien Peter Lin wrote:
> > Hi All,
> >
> > This patch series introduces the Andes PMU extension, which serves
> > the same purpose as Sscofpmf. In this version we use FDT-based
> > probing and the CONFIG_ANDES_CUSTOM_PMU to enable perf sampling
> > and filtering support.
> >
> > Its non-standard local interrupt is assigned to bit 18 in the
> > custom S-mode local interrupt enable/pending registers (slie/slip),
> > while the interrupt cause is (256 + 18).
> >
> > The feature needs the PMU device registered in OpenSBI.
> > The OpenSBI and Linux patches can be found on Andes Technology GitHub
> > - https://github.com/andestech/opensbi/commits/andes-pmu-support-v2
> > - https://github.com/andestech/linux/commits/andes-pmu-support-v3
> >
> > The PMU device tree node used on AX45MP:
> > - https://github.com/andestech/opensbi/blob/andes-pmu-support-v2/docs/pmu_support.md#example-3
> >
> > Tested hardware:
> > - ASUS Tinker-V (RZ/Five, AX45MP single core)
> > - Andes AE350 (AX45MP quad core)
> >
> > Locus Wei-Han Chen (1):
> > riscv: andes: Support symbolic FW and HW raw events
> >
> > Yu Chien Peter Lin (12):
> > riscv: errata: Rename defines for Andes
> > irqchip/riscv-intc: Allow large non-standard hwirq number
> > irqchip/riscv-intc: Introduce Andes IRQ chip
> > dt-bindings: riscv: Add Andes interrupt controller compatible string
> > riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes
> > INTC
> > perf: RISC-V: Eliminate redundant IRQ enable/disable operations
> > RISC-V: Move T-Head PMU to CPU feature alternative framework
> > perf: RISC-V: Introduce Andes PMU for perf event sampling
> > dt-bindings: riscv: Add T-Head PMU extension description
> > dt-bindings: riscv: Add Andes PMU extension description
> > riscv: dts: allwinner: Add T-Head PMU extension
> > riscv: dts: renesas: Add Andes PMU extension
>
> You only sent 5 of these patches FYI.
Hi Conor,
Yeah... I know. The following emails were intercepted automatically
due to our data traffic policy. I will resend the whole series soon.
Best regards,
Peter Lin
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prev parent reply other threads:[~2023-10-23 0:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-22 15:18 [PATCH v3 00/13] Support Andes PMU extension Yu Chien Peter Lin
2023-10-22 15:18 ` [PATCH v3 01/13] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-10-22 15:18 ` [RFC PATCH v3 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number Yu Chien Peter Lin
2023-10-22 15:18 ` [RFC PATCH v3 03/13] irqchip/riscv-intc: Introduce Andes IRQ chip Yu Chien Peter Lin
2023-10-22 15:18 ` [PATCH v3 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2023-10-22 15:18 ` [PATCH v3 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2023-10-22 18:00 ` [PATCH v3 00/13] Support Andes PMU extension Conor Dooley
2023-10-23 0:13 ` Yu-Chien Peter Lin [this message]
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