[PATCH] arm64, irqchip/gic-v3, ACPI: Move MADT GICC enabled check into a helper

[PATCH] arm64, irqchip/gic-v3, ACPI: Move MADT GICC enabled check into a helper

[Russell King]

From: James Morse <james.morse@arm.com>

ACPI, irqchip and the architecture code all inspect the MADT
enabled bit for a GICC entry in the MADT.

The addition of an 'online capable' bit means all these sites need
updating.

Move the current checks behind a helper to make future updates easier.

Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Gavin Shan <gshan@redhat.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
Changes since RFC v2:
 * Remove unnecessary parens
 * Moved earlier in series

Suggestion by Jonathan Cameron that this can be part of a pre-cursor
series. As it doesn't depend on anything else, sending separately so
it can be merged into the aarch64 tree.
---
 arch/arm64/kernel/smp.c       |  2 +-
 drivers/acpi/processor_core.c |  2 +-
 drivers/irqchip/irq-gic-v3.c  | 10 ++++------
 include/linux/acpi.h          |  5 +++++
 4 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 960b98b43506..8c8f55721786 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -520,7 +520,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
 {
 	u64 hwid = processor->arm_mpidr;
 
-	if (!(processor->flags & ACPI_MADT_ENABLED)) {
+	if (!acpi_gicc_is_usable(processor)) {
 		pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
 		return;
 	}
diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c
index 7dd6dbaa98c3..b203cfe28550 100644
--- a/drivers/acpi/processor_core.c
+++ b/drivers/acpi/processor_core.c
@@ -90,7 +90,7 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry,
 	struct acpi_madt_generic_interrupt *gicc =
 	    container_of(entry, struct acpi_madt_generic_interrupt, header);
 
-	if (!(gicc->flags & ACPI_MADT_ENABLED))
+	if (!acpi_gicc_is_usable(gicc))
 		return -ENODEV;
 
 	/* device_declaration means Device object in DSDT, in the
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index f59ac9586b7b..d50d9414f471 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -2380,8 +2380,7 @@ gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
 	u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
 	void __iomem *redist_base;
 
-	/* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
-	if (!(gicc->flags & ACPI_MADT_ENABLED))
+	if (!acpi_gicc_is_usable(gicc))
 		return 0;
 
 	redist_base = ioremap(gicc->gicr_base_address, size);
@@ -2431,7 +2430,7 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
 	 * If GICC is enabled and has valid gicr base address, then it means
 	 * GICR base is presented via GICC
 	 */
-	if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
+	if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) {
 		acpi_data.enabled_rdists++;
 		return 0;
 	}
@@ -2440,7 +2439,7 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
 	 * It's perfectly valid firmware can pass disabled GICC entry, driver
 	 * should not treat as errors, skip the entry instead of probe fail.
 	 */
-	if (!(gicc->flags & ACPI_MADT_ENABLED))
+	if (!acpi_gicc_is_usable(gicc))
 		return 0;
 
 	return -ENODEV;
@@ -2499,8 +2498,7 @@ static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *hea
 	int maint_irq_mode;
 	static int first_madt = true;
 
-	/* Skip unusable CPUs */
-	if (!(gicc->flags & ACPI_MADT_ENABLED))
+	if (!acpi_gicc_is_usable(gicc))
 		return 0;
 
 	maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index afd94c9b8b8a..ebfea7bf663d 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -256,6 +256,11 @@ acpi_table_parse_cedt(enum acpi_cedt_type id,
 int acpi_parse_mcfg (struct acpi_table_header *header);
 void acpi_table_print_madt_entry (struct acpi_subtable_header *madt);
 
+static inline bool acpi_gicc_is_usable(struct acpi_madt_generic_interrupt *gicc)
+{
+	return gicc->flags & ACPI_MADT_ENABLED;
+}
+
 /* the following numa functions are architecture-dependent */
 void acpi_numa_slit_init (struct acpi_table_slit *slit);
 
-- 
2.30.2


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Re: [PATCH] arm64, irqchip/gic-v3, ACPI: Move MADT GICC enabled check into a helper

[Rafael J. Wysocki]

On Mon, Oct 23, 2023 at 3:35 PM Russell King <rmk+kernel@armlinux.org.uk> wrote:
>
> From: James Morse <james.morse@arm.com>
>
> ACPI, irqchip and the architecture code all inspect the MADT
> enabled bit for a GICC entry in the MADT.
>
> The addition of an 'online capable' bit means all these sites need
> updating.
>
> Move the current checks behind a helper to make future updates easier.
>
> Signed-off-by: James Morse <james.morse@arm.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Gavin Shan <gshan@redhat.com>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

for the generic ACPI changes in this patch, but it is knod of
ARM-specific, so I'd prefer ARM64 to pick it up (CC Sudeep).

> ---
> Changes since RFC v2:
>  * Remove unnecessary parens
>  * Moved earlier in series
>
> Suggestion by Jonathan Cameron that this can be part of a pre-cursor
> series. As it doesn't depend on anything else, sending separately so
> it can be merged into the aarch64 tree.
> ---
>  arch/arm64/kernel/smp.c       |  2 +-
>  drivers/acpi/processor_core.c |  2 +-
>  drivers/irqchip/irq-gic-v3.c  | 10 ++++------
>  include/linux/acpi.h          |  5 +++++
>  4 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index 960b98b43506..8c8f55721786 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -520,7 +520,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor)
>  {
>         u64 hwid = processor->arm_mpidr;
>
> -       if (!(processor->flags & ACPI_MADT_ENABLED)) {
> +       if (!acpi_gicc_is_usable(processor)) {
>                 pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid);
>                 return;
>         }
> diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c
> index 7dd6dbaa98c3..b203cfe28550 100644
> --- a/drivers/acpi/processor_core.c
> +++ b/drivers/acpi/processor_core.c
> @@ -90,7 +90,7 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry,
>         struct acpi_madt_generic_interrupt *gicc =
>             container_of(entry, struct acpi_madt_generic_interrupt, header);
>
> -       if (!(gicc->flags & ACPI_MADT_ENABLED))
> +       if (!acpi_gicc_is_usable(gicc))
>                 return -ENODEV;
>
>         /* device_declaration means Device object in DSDT, in the
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index f59ac9586b7b..d50d9414f471 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -2380,8 +2380,7 @@ gic_acpi_parse_madt_gicc(union acpi_subtable_headers *header,
>         u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
>         void __iomem *redist_base;
>
> -       /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
> -       if (!(gicc->flags & ACPI_MADT_ENABLED))
> +       if (!acpi_gicc_is_usable(gicc))
>                 return 0;
>
>         redist_base = ioremap(gicc->gicr_base_address, size);
> @@ -2431,7 +2430,7 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
>          * If GICC is enabled and has valid gicr base address, then it means
>          * GICR base is presented via GICC
>          */
> -       if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) {
> +       if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) {
>                 acpi_data.enabled_rdists++;
>                 return 0;
>         }
> @@ -2440,7 +2439,7 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header,
>          * It's perfectly valid firmware can pass disabled GICC entry, driver
>          * should not treat as errors, skip the entry instead of probe fail.
>          */
> -       if (!(gicc->flags & ACPI_MADT_ENABLED))
> +       if (!acpi_gicc_is_usable(gicc))
>                 return 0;
>
>         return -ENODEV;
> @@ -2499,8 +2498,7 @@ static int __init gic_acpi_parse_virt_madt_gicc(union acpi_subtable_headers *hea
>         int maint_irq_mode;
>         static int first_madt = true;
>
> -       /* Skip unusable CPUs */
> -       if (!(gicc->flags & ACPI_MADT_ENABLED))
> +       if (!acpi_gicc_is_usable(gicc))
>                 return 0;
>
>         maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
> diff --git a/include/linux/acpi.h b/include/linux/acpi.h
> index afd94c9b8b8a..ebfea7bf663d 100644
> --- a/include/linux/acpi.h
> +++ b/include/linux/acpi.h
> @@ -256,6 +256,11 @@ acpi_table_parse_cedt(enum acpi_cedt_type id,
>  int acpi_parse_mcfg (struct acpi_table_header *header);
>  void acpi_table_print_madt_entry (struct acpi_subtable_header *madt);
>
> +static inline bool acpi_gicc_is_usable(struct acpi_madt_generic_interrupt *gicc)
> +{
> +       return gicc->flags & ACPI_MADT_ENABLED;
> +}
> +
>  /* the following numa functions are architecture-dependent */
>  void acpi_numa_slit_init (struct acpi_table_slit *slit);
>
> --
> 2.30.2
>

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Re: [PATCH] arm64, irqchip/gic-v3, ACPI: Move MADT GICC enabled check into a helper

[Sudeep Holla]

On Tue, Oct 24, 2023 at 02:06:55PM +0200, Rafael J. Wysocki wrote:
> On Mon, Oct 23, 2023 at 3:35 PM Russell King <rmk+kernel@armlinux.org.uk> wrote:
> >
> > From: James Morse <james.morse@arm.com>
> >
> > ACPI, irqchip and the architecture code all inspect the MADT
> > enabled bit for a GICC entry in the MADT.
> >
> > The addition of an 'online capable' bit means all these sites need
> > updating.
> >
> > Move the current checks behind a helper to make future updates easier.
> >
> > Signed-off-by: James Morse <james.morse@arm.com>
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > Reviewed-by: Gavin Shan <gshan@redhat.com>
> > Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
> 
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> 
> for the generic ACPI changes in this patch, but it is knod of
> ARM-specific, so I'd prefer ARM64 to pick it up (CC Sudeep).

Thanks Rafael.

The changes looks good to me.

Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>

Catalin,

Can you please up this patch for v6.7 if not too late ? It is simple
refactoring and must not have too much impact.

-- 
Regards,
Sudeep

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Re: [PATCH] arm64, irqchip/gic-v3, ACPI: Move MADT GICC enabled check into a helper

[Catalin Marinas]

On Mon, 23 Oct 2023 14:35:03 +0100, Russell King wrote:
> ACPI, irqchip and the architecture code all inspect the MADT
> enabled bit for a GICC entry in the MADT.
> 
> The addition of an 'online capable' bit means all these sites need
> updating.
> 
> Move the current checks behind a helper to make future updates easier.
> 
> [...]

Applied to arm64 (for-next/misc), thanks!

[1/1] arm64, irqchip/gic-v3, ACPI: Move MADT GICC enabled check into a helper
      https://git.kernel.org/arm64/c/c54e52f84d7a

-- 
Catalin


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