From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 574D8C4332F for ; Thu, 2 Nov 2023 16:00:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4KmHVgPgaN78cbpJUkYVrx8iKBqdmS6MOFNmAZTcDVA=; b=HUazut1M4iw7J4 B4KP3CKsSJ0NT2MHYCi+zQhIIKETu8/zQcRH7orl70sUSk+2C2p8w5yTW+F9qUNGQDBnUmPP74+Ig 6YlaHsHsV/G4yeLwNOYsTW2wK0ohiKG8ZC9sAtP5ZB1rbXGIjhjRKvoMIAkO9+r2lvfOjs/TDyELX gqWBmUIeD129eWwkjN24NRbdNH5YXeGmaqRvIiCw16cjpaUyG6D7Agw2yXqtLZFrsaMvwGmtREB8e 8pppgyIFA5tKRQ/A42bGcBZMxItzqc3CShzgNUzA7RlrzOdQLQ4prZQsZNsAkjR/IZPiResFJarh/ w1Z+lQzR7i/Zt49GFG2w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qya77-009pAe-0v; Thu, 02 Nov 2023 16:00:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qya75-009p89-0n for linux-arm-kernel@lists.infradead.org; Thu, 02 Nov 2023 16:00:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 41DEC2F4; Thu, 2 Nov 2023 09:00:42 -0700 (PDT) Received: from FVFF77S0Q05N.cambridge.arm.com (FVFF77S0Q05N.cambridge.arm.com [10.1.27.166]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 45F3B3F738; Thu, 2 Nov 2023 08:59:58 -0700 (PDT) Date: Thu, 2 Nov 2023 15:59:52 +0000 From: Mark Rutland To: Alexei Starovoitov Cc: Puranjay Mohan , Florent Revest , Daniel Borkmann , Alexei Starovoitov , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Catalin Marinas , bpf , KP Singh , linux-arm-kernel , LKML Subject: Re: [PATCH bpf-next v4 0/3] bpf, arm64: use BPF prog pack allocator in BPF JIT Message-ID: References: <20230626085811.3192402-1-puranjay12@gmail.com> <7e05efe1-0af0-1896-6f6f-dcb02ed8ca27@iogearbox.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231102_090007_345342_1AB3B860 X-CRM114-Status: GOOD ( 14.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 03, 2023 at 12:13:00PM +0100, Mark Rutland wrote: [...] > However, in looking at it I think > there may me a wider potential isssue w.r.t. the way instruction memory gets > reused, because as writtten today the architecture doesn't seem to have a > guarantee on when instruction fetches are completed and therefore when it's > safe to modify instruction memory. Usually we're saved by TLB maintenance, > which this series avoids by design. Just to confirm on this point specifically, per discussions with our architects, the (architectural) execution of an instruction ensures that there are no outstanding fetches for prior instructions. IIUC that will be clarified the next release of the ARM ARM. So as long as we're certain all threads have left the old code (e.g. via a flag, RCU tasks rude synchronization, whatever) before we overwrite slots in the shared buffer, we should be good. We will need to be very careful with the maintenance when installing new code into the shared buffer (e.g. we will require an IPI to all other CPUs), but that should be relatively simple. I'll go review the latest patches with that in mind. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel