From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 776DEC4167B for ; Mon, 4 Dec 2023 17:32:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/WKUkXSiwHXQnVUi69f8ZM2qkE71WYuTm0Quqxhr+Z8=; b=VwbgUYcB2BI0qE glkLGYIyRxuE1PKb0MJdLJBssZoe7hDzjgWAFALCu49dDb2jFkDyEOBZWWa07uNaYrF04g4wCqAFH PqsP4IGdhR4nkg6NMpDnekWyxUsD8Ay1PPq20waTbhNskGA0vQl2gSrJC6Wg6YbLXArIirBPqw/om THMlFhZ3smU7xfwTR0knWra9suh5r1yzjChLpM+bO+vk6oJjfDhesV2fiReeDwdH3+ERYTLUxCXrI 8sl2//ZTwvy2GLkhLUeT7NooT1/mJP0eBR73YcdskMU71X8hpwFHcNBQAKADByiIAlaLt77PepAz/ QWUpMtZ5GRS5DdmB/bCw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rACnV-005CRN-2v; Mon, 04 Dec 2023 17:31:57 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rACnS-005CR2-2w for linux-arm-kernel@lists.infradead.org; Mon, 04 Dec 2023 17:31:56 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id 24769B81148; Mon, 4 Dec 2023 17:31:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3D900C433C7; Mon, 4 Dec 2023 17:31:50 +0000 (UTC) Date: Mon, 4 Dec 2023 17:31:47 +0000 From: Catalin Marinas To: Jason Gunthorpe Cc: Mark Rutland , Leon Romanovsky , Arnd Bergmann , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rdma@vger.kernel.org, llvm@lists.linux.dev, Michael Guralnik , Nathan Chancellor , Nick Desaulniers , Will Deacon Subject: Re: [PATCH rdma-next 1/2] arm64/io: add memcpy_toio_64 Message-ID: References: <20231124122352.GB436702@nvidia.com> <20231127134505.GI436702@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231127134505.GI436702@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231204_093155_271090_5E2A6635 X-CRM114-Status: GOOD ( 31.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 27, 2023 at 09:45:05AM -0400, Jason Gunthorpe wrote: > On Mon, Nov 27, 2023 at 12:42:41PM +0000, Catalin Marinas wrote: > > > > What's the actual requirement here? Is this just for performance? > > > > > > Yes, just performance. > > > > Do you have any rough numbers (percentage)? It's highly > > microarchitecture-dependent until we get the ST64B instruction. > > The current C code is an open coded store loop. The kernel does 250 > tries and measures if any one of them succeeds to combine. > > On x86, and older ARM cores we see that 100% of the time at least 1 in > 250 tries succeeds. > > With the new CPU cores we see more like 9 out of 10 time there are 0 > in 250 tries that succeed. Ie we can go thousands of times without > seeing any successful WC combine. > > The STP block brings it back to 100% of the time 1 in 250 succeed. That's a bit confusing to me: 1 in 250 succeeding is still pretty rare. But I guess what your benchmark says is that at least 1 succeeded to write-combine and it might as well be all 250 tries. It's more interesting to see if there's actual performance gain in real-world traffic, not just some artificial benchmark (I may have misunderstood your numbers above). > However, in userspace we have long been using ST4 to create a > single-instruction 64 byte store on ARM64. As far as I know this is > highly reliable. I don't have direct data on the STP configuration. Personally I'd optimise the mempcy_toio() arm64 implementation to do STPs if the alignment is right (like we do for classic memcpy()). There's a slight overhead for alignment checking but I suspect it would be lost as long as you can get the write-combining. Not sure whether the interspersed reads in memcpy_toio() would somehow prevent the write-combining. A memcpy_toio_64() can use the new ST64B instruction if available or fall back to memcpy_toio() on arm64. It should also have the DGH instruction (io_stop_wc()) but only if falling back to classic memcpy_toio(). We don't need DGH with ST64B. > > More of a bike-shedding, I wonder whether the __iowrite*_copy() > > semantics are better suited for what you need in terms of ordering (not > > that mempcy_toio() to Normal NC memory gives us any ordering). > > I have the same remark I gave to Niklas, this does not require > alignment or an exact 64 byte size. It was clearly made to support WC > stores since Pathscale did it, but I don't see this mapping nicely to > the future 64 byte store instructions are we getting. As above, I'd suggest just using memcpy_toio() as a fallback if ST64B is not available. > We could name it __iowrite512_copy() if that makes more sense? I've been thinking at the __iowrite*_copy() and these also take a 'count' argument. I assume in this instance we don't really need one, so it's just additional overhead (more like API clutter, I doubt it makes much difference for performance). I'd say just stick to the mempcy_toio_64() but have the io_stop_wc() inside this function as we won't need it with ST64B. Well, unless someone has a better name for this function. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel