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Mon, 4 Dec 2023 17:38:54 -0800 Date: Mon, 4 Dec 2023 17:38:52 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: , Joerg Roedel , , Robin Murphy , Will Deacon , Michael Shavit , Shameerali Kolothum Thodi Subject: Re: [PATCH v2 04/19] iommu/arm-smmu-v3: Make STE programming independent of the callers Message-ID: References: <0-v2-de8b10590bf5+400-smmuv3_newapi_p1_jgg@nvidia.com> <4-v2-de8b10590bf5+400-smmuv3_newapi_p1_jgg@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4-v2-de8b10590bf5+400-smmuv3_newapi_p1_jgg@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECDA:EE_|MN0PR12MB6029:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c24206b-2afd-4407-fb59-08dbf532f9a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: d4yz0uFR8wDSiyUg0t2DV9EJtV23fOaB/yYiCqPXEiKbNlJ/yyzigB432lBwvs3ds6YVKp4QziIlInrjXZvZPXxd+WnfchfuJmHpRE1KvY35Ygn+5rQbhYDS73Drs0u/Sl+NyS1zc8lYid0J34QzSuzUpMWVsjNzz6+ZtmYmIubO3Bs2Y/np9ZHQfpgzKMf7slybtxH7Pen/0EAbGmYd9mIpak5LrjgiA0ibAYeaUmMu2IRGhRggd198FLt7A/CVJ823Z/S1h4toes3zJzOjl8BflYpNarBEyKFRH6RbpJOWVpqxcUoedg/lTRjmiKCWF0AFNQ801SgKABugbBLX7B3pvSlUfr+UdHUBYkf4BPVJt9g//dFdYks4sAM7XQ+ow9xyugCnFyAvpPEDJU5PACAl8eNhZ13xMawbOxaOZTj9HLlO0KNLsolJzPcOree2rETGOTbNDA3v0WmZWE5hs41j0YuB7Pcsv8O8GI1ysIGbG0+Bo05W+nOaigjSqyLewve4bi/ZEvTC/m8nLEVZ6g8oEIgMk7yKEnVNmTdOe4z6AxWN43ma/QOl29WmtGCkGm+rqG9ln/hjE4kC26Ym9V7yuN1JvPxg9I2U6+/HyokV6r5YvMvn/sXo2VKS28ioOBQy9GIMUwEV4O8S498JWplNYIwNzPBLXFkMSZ+KgEAqeOQId0rcZ2KYKHvkV247bw5RDQYmTzZXut9P3wm6iFNC+l81RdWPt1XEfVSDiByV6amWwu3dGkAy5CyG5fTU X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(39860400002)(136003)(396003)(230922051799003)(186009)(82310400011)(1800799012)(451199024)(64100799003)(36840700001)(40470700004)(46966006)(70586007)(54906003)(70206006)(316002)(6636002)(478600001)(40460700003)(5660300002)(41300700001)(2906002)(33716001)(86362001)(6862004)(4326008)(8936002)(8676002)(36860700001)(40480700001)(47076005)(83380400001)(356005)(7636003)(55016003)(26005)(426003)(82740400003)(336012)(9686003);DIR:OUT;SFP:1101; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 13, 2023 at 01:53:11PM -0400, Jason Gunthorpe wrote: > As the comment in arm_smmu_write_strtab_ent() explains, this routine has > been limited to only work correctly in certain scenarios that the caller > must ensure. Generally the caller must put the STE into ABORT or BYPASS > before attempting to program it to something else. > > The next patches/series are going to start removing some of this logic > from the callers, and add more complex state combinations than currently. > > Thus, consolidate all the complexity here. Callers do not have to care > about what STE transition they are doing, this function will handle > everything optimally. > > Revise arm_smmu_write_strtab_ent() so it algorithmically computes the > required programming sequence to avoid creating an incoherent 'torn' STE > in the HW caches. The update algorithm follows the same design that the > driver already uses: it is safe to change bits that HW doesn't currently > use and then do a single 64 bit update, with sync's in between. > > The basic idea is to express in a bitmask what bits the HW is actually > using based on the V and CFG bits. Based on that mask we know what STE > changes are safe and which are disruptive. We can count how many 64 bit > QWORDS need a disruptive update and know if a step with V=0 is required. > > This gives two basic flows through the algorithm. > > If only a single 64 bit quantity needs disruptive replacement: > - Write the target value into all currently unused bits > - Write the single 64 bit quantity > - Zero the remaining different bits > > If multiple 64 bit quantities need disruptive replacement then do: > - Write V=0 to QWORD 0 > - Write the entire STE except QWORD 0 > - Write QWORD 0 > > With HW flushes at each step, that can be skipped if the STE didn't change > in that step. > > At this point it generates the same sequence of updates as the current > code, except that zeroing the VMID on entry to BYPASS/ABORT will do an > extra sync (this seems to be an existing bug). > > Going forward this will use a V=0 transition instead of cycling through > ABORT if a hitfull change is required. This seems more appropriate as ABORT > will fail DMAs without any logging, but dropping a DMA due to transient > V=0 is probably signaling a bug, so the C_BAD_STE is valuable. > > Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel