Re: [PATCH v2 15/19] iommu/arm-smmu-v3: Add a global static IDENTITY domain

From: Nicolin Chen <nicolinc@nvidia.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: <iommu@lists.linux.dev>, Joerg Roedel <joro@8bytes.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	Michael Shavit <mshavit@google.com>,
	Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Subject: Re: [PATCH v2 15/19] iommu/arm-smmu-v3: Add a global static IDENTITY domain
Date: Tue, 5 Dec 2023 09:25:59 -0800	[thread overview]
Message-ID: <ZW9dJ1yzsdCjpMGm@Asurada-Nvidia> (raw)
In-Reply-To: <20231205143742.GB2787277@nvidia.com>

On Tue, Dec 05, 2023 at 10:37:42AM -0400, Jason Gunthorpe wrote:
> On Mon, Dec 04, 2023 at 08:28:23PM -0800, Nicolin Chen wrote:
> 
> > > +static int arm_smmu_attach_dev_ste(struct device *dev,
> > > +				   struct arm_smmu_ste *ste)
> > > +{
> > > +	struct arm_smmu_master *master = dev_iommu_priv_get(dev);
> > > +
> > > +	if (arm_smmu_master_sva_enabled(master))
> > > +		return -EBUSY;
> > > +
> > > +	/*
> > > +	 * Do not allow any ASID to be changed while are working on the STE,
> > > +	 * otherwise we could miss invalidations.
> > > +	 */
> > > +	mutex_lock(&arm_smmu_asid_lock);
> > > +
> > > +	/*
> > > +	 * The SMMU does not support enabling ATS with bypass/abort. When the
> > > +	 * STE is in bypass (STE.Config[2:0] == 0b100), ATS Translation Requests
> > > +	 * and Translated transactions are denied as though ATS is disabled for
> > > +	 * the stream (STE.EATS == 0b00), causing F_BAD_ATS_TREQ and
> > > +	 * F_TRANSL_FORBIDDEN events (IHI0070Ea 5.2 Stream Table Entry).
> > > +	 */
> > > +	arm_smmu_detach_dev(master);
> > > +
> > > +	arm_smmu_install_ste_for_dev(master, ste);
> > > +	mutex_unlock(&arm_smmu_asid_lock);
> > > +
> > > +	/*
> > > +	 * This has to be done after removing the master from the
> > > +	 * arm_smmu_domain->devices to avoid races updating the same context
> > > +	 * descriptor from arm_smmu_share_asid().
> > > +	 */
> > > +	if (master->cd_table.cdtab)
> > > +		arm_smmu_write_ctx_desc(master, IOMMU_NO_PASID, NULL);
> >  
> > This arm_smmu_write_ctx_desc was previously within the asid lock
> > protection, yet now it's moved out of that?
> 
> Yes, arm_smmu_write_ctx_desc() updates a CD table entry and that does
> not need ASID lock protection. The ASID lock exists because of the BTM
> code rewriting STEs asyncronously.

I see. Thanks for elaborating. For this patch:

Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>

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