From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: <acme@kernel.org>, <adrian.hunter@intel.com>,
<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
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Subject: Re: [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension
Date: Wed, 29 Nov 2023 17:34:30 +0800 [thread overview]
Message-ID: <ZWcFpjLbAf1-YtLs@APC323> (raw)
In-Reply-To: <20231123-coping-revenue-be284a351c9d@wendy>
Hi Conor,
On Thu, Nov 23, 2023 at 02:58:55PM +0000, Conor Dooley wrote:
> On Wed, Nov 22, 2023 at 08:12:33PM +0800, Yu Chien Peter Lin wrote:
> > xtheadpmu stands for T-Head Performance Monitor Unit extension.
> > Based on the added T-Head PMU ISA string, the SBI PMU driver
> > will make use of the non-standard irq source.
>
> Allwinner aren't the only ones using T-Head CPUs that the previous
> m*id pmu detection code would have matched on. I think the first three
> files below will also need to be updated:
>
> rg -l "thead,c[0-9]*\b[^-]" arch/riscv/boot/dts/
> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> arch/riscv/boot/dts/thead/th1520.dtsi
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
That's really helpful, I'll add these .dtsi files in the patchset v5.
Thanks,
Peter Lin
> Cheers,
> Conor.
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next prev parent reply other threads:[~2023-11-29 9:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20231122121235.827122-1-peterlin@andestech.com>
[not found] ` <20231122121235.827122-6-peterlin@andestech.com>
2023-11-22 16:36 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Geert Uytterhoeven
[not found] ` <20231122121235.827122-10-peterlin@andestech.com>
2023-11-22 21:14 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Guo Ren
2023-11-29 8:48 ` Yu-Chien Peter Lin
[not found] ` <IA1PR20MB49537364BDF1ADE185CA8FE4BB82A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-11-30 9:21 ` Yu-Chien Peter Lin
[not found] ` <IA1PR20MB4953A05B9162AA2659DE78A5BB82A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-11-30 12:58 ` Conor Dooley
[not found] ` <IA1PR20MB495378652B09B37E92D8BB04BB82A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-12-01 0:40 ` Conor Dooley
[not found] ` <IA1PR20MB4953460FE5BF431DD32CD860BB81A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-11-23 14:48 ` Conor Dooley
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 12:33 ` Conor Dooley
[not found] ` <20231122121235.827122-8-peterlin@andestech.com>
2023-11-22 21:16 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Guo Ren
2023-11-23 14:45 ` Conor Dooley
[not found] ` <20231122121235.827122-5-peterlin@andestech.com>
2023-11-23 14:38 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Conor Dooley
[not found] ` <CA+V-a8t+vgrwDe9OxqMNHdcVX+qq76DuskF0ETCri4VeP-FAbg@mail.gmail.com>
2023-11-29 6:43 ` Yu-Chien Peter Lin
[not found] ` <20231122121235.827122-12-peterlin@andestech.com>
2023-11-22 21:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Guo Ren
2023-11-23 14:58 ` Conor Dooley
2023-11-29 9:34 ` Yu-Chien Peter Lin [this message]
[not found] ` <20231122121235.827122-3-peterlin@andestech.com>
[not found] ` <871qbwsn9h.ffs@tglx>
2023-12-12 10:17 ` [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number Yu-Chien Peter Lin
[not found] ` <20231122121235.827122-4-peterlin@andestech.com>
[not found] ` <87y1e4r8db.ffs@tglx>
2023-12-12 10:28 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu-Chien Peter Lin
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