From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEC24C46CCD for ; Sat, 16 Dec 2023 12:45:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=zwDw0vyOMSZkCqC1yaZM9vEHFh7/EfeCF6cQubZxxV8=; b=McWXBeklQiJiJf KW0xuc0KgywUp5MDhQPiWVFGyX4F/lb0CQIGJYLTUpLLCqATFwdjKks2njyN1gUmZ7xswVqI26mbr VeQpp3XDUjxaX8HVUgle82O/XrhzZf9P0XO5v6UrNr8sFXqtMgSc4dv3+txoYcPuAY0c/MutfO5wD XHjc96csh3HQtrFTZaxseHKsO3ErfFPKFv+NdnJ0yNiivz5xo+k2oCKOvnFizc8tYffnqMX3Sy5TA Q45hMNbIbUvHbAAQIp1NrEDyHuI1CWopxtytPVRnr91VmrmZc/pT9NlVvRr4YlS3kmrSId6S38m8P GAgRV1L7KIiXXwYanBLw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rEU2J-0063qs-2N; Sat, 16 Dec 2023 12:44:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rEU2G-0063qS-0B for linux-arm-kernel@lists.infradead.org; Sat, 16 Dec 2023 12:44:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4D20E2F4; Sat, 16 Dec 2023 04:45:29 -0800 (PST) Received: from FVFF77S0Q05N (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 78DC73F762; Sat, 16 Dec 2023 04:44:42 -0800 (PST) Date: Sat, 16 Dec 2023 12:44:33 +0000 From: Mark Rutland To: James Clark , will@kernel.org, catalin.marinas@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-next@vger.kernel.org, u.kleine-koenig@pengutronix.de, Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , Anshuman Khandual , Suzuki K Poulose , linux-kernel@vger.kernel.org, llvm@lists.linux.dev Subject: Re: [PATCH v2 1/1] arm: perf: Fix ARCH=arm build with GCC Message-ID: References: <20231215175648.3397170-1-james.clark@arm.com> <20231215175648.3397170-2-james.clark@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231215175648.3397170-2-james.clark@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231216_044452_160015_0478DBEB X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 15, 2023 at 05:56:48PM +0000, James Clark wrote: > LLVM ignores everything inside the if statement and doesn't generate > errors, but GCC doesn't ignore it, resulting in the following error: > > drivers/perf/arm_pmuv3.c: In function 'armv8pmu_write_evtype': > include/linux/bits.h:34:29: error: left shift count >= width of type [-Werror=shift-count-overflow] > 34 | (((~UL(0)) - (UL(1) << (l)) + 1) & \ > > Fix it by using GENMASK_ULL which doesn't overflow on arm32 (even though > the value is never used there). It would be nice if this could explain the overflow problem, i.e. | The GENMASK() macro creates masks of type unsigned long, and we use this to | geenrate the ARMV8_PMU_EVTYPE_TH and ARMV8_PMU_EVTYPE_TC constants. These | include bits above bit 31, and generating these requires shifting more than the | size of unsigned long on 32-bit ARM. | | Consequently when building for 32-bit arm, GCC warns about their use: | | drivers/perf/arm_pmuv3.c: In function 'armv8pmu_write_evtype': | include/linux/bits.h:34:29: error: left shift count >= width of type [-Werror=shift-count-overflow] | 34 | (((~UL(0)) - (UL(1) << (l)) + 1) & \ | | ... though LLVM does not warn as the actual usage is not reachable on 32-bit | ARM due to `if (IS_ENABLED(...)` checks. | | Avoid the warning by using GENMACK_ULL(), which doesn't overflow on 32-bit arm. > Fixes: 3115ee021bfb ("arm64: perf: Include threshold control fields in PMEVTYPER mask") > Reported-by: Uwe Kleine-K"onig > Closes: https://lore.kernel.org/linux-arm-kernel/20231215120817.h2f3akgv72zhrtqo@pengutronix.de/ > Signed-off-by: James Clark Thanks for this! Acked-by: Mark Rutland Will, Catalin, the broken commit is queued in the arm64 for-next/perf branch (and merged into for-next/core); is this something we can easily fold in? Mark. > --- > include/linux/perf/arm_pmuv3.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h > index 0f4d62ef3a9a..46377e134d67 100644 > --- a/include/linux/perf/arm_pmuv3.h > +++ b/include/linux/perf/arm_pmuv3.h > @@ -234,8 +234,8 @@ > * PMXEVTYPER: Event selection reg > */ > #define ARMV8_PMU_EVTYPE_EVENT GENMASK(15, 0) /* Mask for EVENT bits */ > -#define ARMV8_PMU_EVTYPE_TH GENMASK(43, 32) > -#define ARMV8_PMU_EVTYPE_TC GENMASK(63, 61) > +#define ARMV8_PMU_EVTYPE_TH GENMASK_ULL(43, 32) /* arm64 only */ > +#define ARMV8_PMU_EVTYPE_TC GENMASK_ULL(63, 61) /* arm64 only */ > > /* > * Event filters for PMUv3 > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel